X1288V14I-4.5AT1 Intersil, X1288V14I-4.5AT1 Datasheet
X1288V14I-4.5AT1
Specifications of X1288V14I-4.5AT1
Related parts for X1288V14I-4.5AT1
X1288V14I-4.5AT1 Summary of contents
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... Timer Reset CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 trademark of Philips. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X1288 FN8102.3 Battery Time Switch ...
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... X1288V14Z-2.7* (Note) X1288V ZF X1288V14I-2.7* X1288V G X1288V14IZ-2.7* (Note) X1288V ZG *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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PIN ASSIGNMENTS Pin Number SOIC TSSOP Symbol X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1288 to supply a timebase for the real time clock. ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage and PHZ/IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin ...
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The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t that initiates a nonvolatile write cycle clock cycles after any start that is not followed by the ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V V slew rate should be between 0.2mV/µsec and 50mV/µsec. CC (2) Typical ...
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V Programming Timing Diagram TRIP TRIP RESET VPS SCL SDA AEh V Programming Parameters TRIP Parameter t V Program Enable Voltage Setup time VPS TRIP ...
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The device offers a backup power input pin. This V pin allows the device to be backed up by battery or SuperCap. The entire X1288 device is fully operational from 2.7 to 5.5 volts and the clock/calendar portion of the ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. these parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks capacitance to tune oscillator frequency from +116 ppm to – ...
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Table 1. Clock/Control Memory Map Reg Addr. Type Name 7 003F Status SR BAT 0037 RTC SSEC SS23 (SRAM) 0036 DW 0 0035 YR Y23 0034 MO 0 0033 DT 0 0032 HR MIL 0031 MN 0 0030 SC 0 ...
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MIL=1), DT (Date 31, MO (Month 12, YR (Year 99. The SSEC register is read-only. Date of the Week Register (DW) This register provides ...
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CONTROL REGISTERS The Control Bits and Registers, described under this section, are nonvolatile. Block Protect Bits - BP2, BP1, BP0 The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to ...
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... ATR value. See Application section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/ control register requires the following steps: – ...
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RSP t <t RSP SCL SDA RESET Start Note: All inputs are ignored during the active reset period (t LOW VOLTAGE RESET OPERATION When a power failure occurs, and the voltage to the part drops below a fixed v ...
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V TRIP PURST t R RESET FIGURE 5. POWER-ON RESET AND LOW VOLTAGE RESET RESET SCL SDA AEh Note: BP0, BP1, BP2 must be disabled. FIGURE 6. ...
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SCL SDA FIGURE 9. VALID START AND STOP CONDITIONS SCL from Master Data Output from Transmitter Data Output from Receiver Start FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER Device Identifier Array CCR 0 ...
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Signals from the Master SDA Bus Signals From The Slave . 7 Bytes Address = 6 FIGURE 13. WRITING 30 BYTES TO A 128-BYTE MEMORY PAGE STARTING AT ADDRESS 105 SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus ...
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The device will terminate further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known ...
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S t Signals from a the Master Slave r Address t SDA Bus 1 Signals from the Slave ation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 14 for the address, acknowledge, and data ...
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Byte load completed by issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) NO ACK returned? YES NO nonvolatile write Cycle complete. Continue command sequence? YES Continue normal Read or Write command sequence PROCEED FIGURE ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation fea- ture is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in incre- ments of 10ppm ...
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... XTAL1 32.768kGz FIGURE 19. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8 The X1 and X2 connections to the crystal are to be kept as short as possible. A thick ground trace around the crystal is advised to minimize noise intrusion, but ground near the X1 and X2 pins should be avoided as it will add to the load capacitance at those pins ...
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... Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where Vcc may disappear intermittently for short periods of time. ...
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The summary of conditions for backup battery operation is given in Table 9: Table 9. Battery Backup Operation 1. Example Application, Vcc=5V, Vback=3.0V Condition a. Normal Operation b. Vcc on with no battery c. Backup Mode 2. Example Application, Vcc=3.3V,Vback=3.0V ...
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PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 26 X1288 14-Lead Plastic, TSSOP, Package Code V14 .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...