AD9235BRUZ-40 Analog Devices Inc, AD9235BRUZ-40 Datasheet - Page 15

• Manufacturer Part Number: AD9235BRUZ-40
• Description: IC ADC 12BIT 40MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9235BRUZ-40

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 3
• Power Dissipation (max): 165mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 40MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9235BCP-65EBZ - BOARD EVAL FOR AD9235BCP-65AD9235BCP-40EBZ - BOARD EVAL FOR AD9235BCP-40AD9235BCP-20EBZ - BOARD EVAL FOR AD9235BCP-20AD9235-65PCB - BOARD EVAL FOR AD9235-65AD9235-40PCB - BOARD EVAL FOR AD9235-40AD9235-20PCB - BOARD EVAL FOR AD9235-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLYING THE AD9235
THEORY OF OPERATION
The AD9235 architecture consists of a front end SHA followed
by a pipelined switched capacitor ADC. The pipelined ADC is
divided into three sections, consisting of a 4-bit first stage
followed by eight 1.5-bit stages and a final 3-bit flash. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stages. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge
of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 34. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
Referring to Figure 33, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth.
Rev. C | Page 15 of 40
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
REFT = ½(AVDD + VREF)
REFB = ½(AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
90
85
80
75
70
65
60
55
50
VIN+
VIN–
0
Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level
C
C
PAR
PAR
0.5
Figure 33. Switched-Capacitor SHA Input
SNR 35MHz 2V DIFF
T
T
COMMON-MODE LEVEL (V)
1.0
SNR 2.5MHz 2V DIFF
5pF
THD 35MHz 2V DIFF
5pF
1.5
T
T
2.0
THD 2.5MHz 2V DIFF
2.5
H
H
AD9235
3.0
–90
–85
–80
–75
–70
–65
–60
–55
–50