AD9235BRUZ-40 Analog Devices Inc, AD9235BRUZ-40 Datasheet - Page 17

• Manufacturer Part Number: AD9235BRUZ-40
• Description: IC ADC 12BIT 40MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9235BRUZ-40

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 3
• Power Dissipation (max): 165mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 40MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9235BCP-65EBZ - BOARD EVAL FOR AD9235BCP-65AD9235BCP-40EBZ - BOARD EVAL FOR AD9235BCP-40AD9235BCP-20EBZ - BOARD EVAL FOR AD9235BCP-20AD9235-65PCB - BOARD EVAL FOR AD9235-65AD9235-40PCB - BOARD EVAL FOR AD9235-40AD9235-20PCB - BOARD EVAL FOR AD9235-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated by
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9235. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 38, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
SNR Degradation = −20 × log
I
DRVDD
= V
DRVDD
INPUT
CLK
× C
) due only to aperture jitter (t
/2. In practice, the DRVDD current is
LOAD
× f
CLK
× N
10
[2π × f
J
, represents the root-
INPUT
× t
J
]
J
) can be
Rev. C | Page 17 of 40
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capaci-
tive load presented to the output drivers. The data in Figure 38
was taken with a 5 pF load on each output driver.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9235 into its normal
operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 sec to fully discharge the
reference buffer decoupling capacitors and 3 ms to restore full
operation.
325
300
275
250
225
200
175
150
125
100
75
50
0
Figure 38. Total Power vs. Sample Rate with f
AD9235-20
10
AD9235-40
20
SAMPLE RATE (MSPS)
AD9235-65
30
40
50
IN
= 10 MHz
60
AD9235