AD9235BRUZ-40 Analog Devices Inc, AD9235BRUZ-40 Datasheet - Page 16

• Manufacturer Part Number: AD9235BRUZ-40
• Description: IC ADC 12BIT 40MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9235BRUZ-40

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 3
• Power Dissipation (max): 165mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 40MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9235BCP-65EBZ - BOARD EVAL FOR AD9235BCP-65AD9235BCP-40EBZ - BOARD EVAL FOR AD9235BCP-40AD9235BCP-20EBZ - BOARD EVAL FOR AD9235BCP-20AD9235-65PCB - BOARD EVAL FOR AD9235-65AD9235-40PCB - BOARD EVAL FOR AD9235-40AD9235-20PCB - BOARD EVAL FOR AD9235-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9235
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section. Maxi-
mum SNR performance is achieved with the AD9235 set to the
largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age. The minimum and maximum common-mode input levels
are defined as:
The minimum common-mode input level allows the AD9235 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9235 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9235-40 and AD9235-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9235 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9235. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
VCM
VCM
0.1µF
1Vp-p
Figure 35. Differential Input Configuration Using the AD8138
MIN
MAX
1kΩ
1kΩ
49.9Ω
= VREF/2
= (AVDD + VREF)/2
499Ω
523Ω
499Ω
499Ω
AD8138
15pF
15pF
22Ω
22Ω
VIN+
VIN–
AD9235
AGND
AVDD
Rev. C | Page 16 of 40
differential transformer coupling is the recommended input
configuration, as shown in Figure 36.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is degra-
dation in SFDR and in distortion performance due to the large
input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 37 details a typical single-
ended input configuration.
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result, may be sensi-
tive to clock duty cycle. Commonly a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance char-
acteristics. The AD9235 contains a clock duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the perform-
ance of the AD9235. As shown in Figure 30, noise and distor-
tion performance are nearly flat over a 30% range of duty cycle.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
2Vp-p
2Vp-p
Figure 36. Differential Transformer-Coupled Configuration
10µF
Figure 37. Single-Ended Input Configuration
49.9Ω
49.9Ω
0.1µF
0.33µF
0.1µF
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
15pF
15pF
22Ω
22Ω
15pF
22Ω
22Ω
15pF
VIN+
VIN–
VIN+
VIN–
AD9235
AD9235
AGND
AGND
AVDD
AVDD