AD9235BRUZ-40 Analog Devices Inc, AD9235BRUZ-40 Datasheet - Page 18

• Manufacturer Part Number: AD9235BRUZ-40
• Description: IC ADC 12BIT 40MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9235BRUZ-40

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Number Of Converters: 3
• Power Dissipation (max): 165mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Sampling Rate: 40MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9235BCP-65EBZ - BOARD EVAL FOR AD9235BCP-65AD9235BCP-40EBZ - BOARD EVAL FOR AD9235BCP-40AD9235BCP-20EBZ - BOARD EVAL FOR AD9235BCP-20AD9235-65PCB - BOARD EVAL FOR AD9235-65AD9235-40PCB - BOARD EVAL FOR AD9235-40AD9235-20PCB - BOARD EVAL FOR AD9235-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9235
Table 7. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
As detailed in Table 8, the data format can be selected for either
offset binary or twos complement.
Timing
The AD9235 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (t
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9235;
these transients can detract from the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9235, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
Internal Reference Connection
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possi-
ble states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 39), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 40, the switch is again set to the
PD
) after the rising edge of the clock signal. Refer to
SENSE Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
Internal Switch Position
N/A
SENSE
SENSE
Internal Divider
Rev. C | Page 18 of 40
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
10µF
10µF
Resulting VREF (V)
N/A
0.5
0.5 × (1 + R2/R1)
1.0
+
VREF = 0.5 × (1 + R2/R1)
+
SENSE
0.1µF
0.1µF
SENSE
Figure 40. Programmable Reference Configuration
R2
VREF
R1
VREF
VIN+
VIN+
VIN–
VIN–
Figure 39. Internal Reference Configuration
SELECT
SELECT
LOGIC
LOGIC
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF (See Figure 40)
2.0
AD9235
AD9235
CORE
CORE
ADC
ADC
0.5V
0.5V
REFT
REFB
REFT
REFB
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+
+
10µF
10µF