AD7760BSVZ Analog Devices Inc, AD7760BSVZ Datasheet

IC ADC 24BIT 2.5MSPS 64TQFP

AD7760BSVZ

Manufacturer Part Number
AD7760BSVZ
Description
IC ADC 24BIT 2.5MSPS 64TQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7760BSVZ

Data Interface
Parallel
Number Of Bits
24
Sampling Rate (per Second)
2.5M
Number Of Converters
1
Power Dissipation (max)
958mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP Exposed Pad
Resolution (bits)
24bit
Sampling Rate
2.5MSPS
Input Channel Type
Differential
Supply Voltage Range - Digital
2.375V To 2.625V
Supply Current
49mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FEATURES
120 dB dynamic range at 78 kHz output data rate
100 dB dynamic range at 2.5 MHz output data rate
112 dB SNR at 78 kHz output data rate
100 dB SNR at 2.5 MHz output data rate
2.5 MHz maximum fully filtered output word rate
Programmable oversampling rate (8× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or
Modulator output mode
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The AD7760 is a high performance, 24-bit Σ-Δ analog-to-digital
converter (ADC). It combines wide input bandwidth and high
speed with the benefits of Σ-Δ conversion to achieve a perfor-
mance of 100 dB SNR at 2.5 MSPS, making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced antialiasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7760 a compact, highly integrated
data acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable decimation
rates, and the digital FIR filter can be adjusted if the default
characteristics are not appropriate for the application. The
AD7760 is ideal for applications demanding high SNR
without a complex front-end signal processing design.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low-
pass filters, with the final filter having default or user-programmable
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
user-programmable coefficients
Sigma-Delta ADC with On-Chip Buffer
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7760.
The reference voltage supplied to the AD7760 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.
The AD7760 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No.
AD7762
AD7763
RESET
MCLK
V
SYNC
REF+
CS
BUF
2.5 MSPS, 24-Bit, 100 dB
AD7760
FUNCTIONAL BLOCK DIAGRAM
RD/WR
Description
24-bit, 625 kSPS, 109 dB, Σ-Δ parallel interface
24-bit, 625 kSPS, 109 dB, Σ-Δ serial interface
OFFSET AND GAIN
CONTROL LOGIC
REGISTERS
DRDY
I/O
DIFF
DB0 TO DB15
©2006 Analog Devices, Inc. All rights reserved.
Figure 1.
V
IN
V
IN
RECONSTRUCTION
PROGRAMMABLE
+
MODULATOR
DECIMATION
FIR FILTER
MULTIBIT
ENGINE
Σ-Δ
AD7760
www.analog.com
AV
AV
AV
AV
DECAPA/B
R
AGND
V
DV
DGND
DRIVE
BIAS
DD
DD
DD
DD
DD
1
2
3
4

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AD7760BSVZ Summary of contents

Page 1

FEATURES 120 dB dynamic range at 78 kHz output data rate 100 dB dynamic range at 2.5 MHz output data rate 112 dB SNR at 78 kHz output data rate 100 dB SNR at 2.5 MHz output data rate 2.5 ...

Page 2

AD7760 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration ...

Page 3

REVISION HISTORY 8/06—Rev Rev. A Updated Package Option................................................... Universal Change to Features............................................................................1 Changes to Specifications.................................................................4 Changes to Absolute Maximum Ratings........................................8 Changes to Terminology Section ..................................................11 Added Figure 36 Through Figure 39 ............................................17 Added Modulator Data Output Mode Section ...

Page 4

AD7760 SPECIFICATIONS 2 DRIVE DD the on-chip amplifier with components as shown in Table 8, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Decimate by 256 ...

Page 5

Parameter ANALOG INPUT Differential Input Voltage Input Capacitance REFERENCE INPUT/OUTPUT V Input Voltage REF V Input DC Leakage Current REF V Input Capacitance REF POWER DISSIPATION Total Power Dissipation Standby Mode POWER REQUIREMENTS AV 1 (Modulator Supply ...

Page 6

AD7760 TIMING SPECIFICATIONS 2 DRIVE DD Table 3. Parameter Limit MIN MAX f 1 MCLK 40 f 500 ICLK ...

Page 7

TIMING DIAGRAMS DRDY CS RD/WR D[0:15] CS RD/ D[0:15 DATA MSW Figure 2. Filtered Output—Parallel Interface Timing Diagram REGISTER ADDRESS ...

Page 8

AD7760 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameters GND GND GND GND DRIVE – to ...

Page 9

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND MCLKGND MCLK AV AGND2 AV AGND1 DECAPA REFGND V AGND4 AV AGND2 AV AV AGND2 Table 5. Pin Function Descriptions Pin No. Mnemonic Description 2.5 V Power Supply for Modulator. ...

Page 10

AD7760 Pin No. Mnemonic Description 30 DECAPB Decoupling Pin capacitor must be inserted between this pin and AGND3 Bias Current Setting Pin. A resistor must be inserted between this pin and AGND. For more details, ...

Page 11

TERMINOLOGY Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed ...

Page 12

AD7760 TYPICAL PERFORMANCE CHARACTERISTICS 2 DRIVE DD FFTs are generated from 65,536 samples using a 7-term Blackman-Harris window. 0 –25 –50 –75 –100 –125 –150 –175 ...

Page 13

FREQUENCY (kHz) Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 8× Decimation 0 –25 –50 –75 –100 –125 –150 –175 –200 0 250 500 ...

Page 14

AD7760 0 –25 –50 –75 –100 –125 –150 –175 –200 0 250 500 750 FREQUENCY (kHz) Figure 17. Normal Mode FFT, 1 MHz, −6 dB Input Tone, 8× Decimation 0 TONE A: 999.75kHz –25 TONE B: 1.00025MHz –50 –75 –100 ...

Page 15

TONE A: 999.75kHz TONE B: 1.00025MHz –20 THIRD-ORDER IMD: –89.15dB –40 –60 –80 –100 –120 –140 –160 995 997 999 1001 FREQUENCY (kHz) Figure 23. Normal Mode IMD, 1 MHz Center Frequency, 8× Decimation 100.5 NORMAL MODE 100.0 99.5 ...

Page 16

AD7760 4500 4000 3500 3000 2500 2000 1500 1000 500 0 8385222 8385238 8385254 24-BIT CODE Figure 29. Normal Mode, 24-Bit Histogram, 256× Decimation 600 500 400 300 200 100 0 8385016 8385116 8385216 8385316 24-BIT CODE Figure 30. Normal ...

Page 17

CODE Figure 35. 24-Bit DNL ICLK FREQUENCY (MHz) Figure 36. AI ...

Page 18

AD7760 THEORY OF OPERATION The AD7760 employs a Σ-Δ conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate ...

Page 19

MODULATOR DATA OUTPUT MODE Operating the AD7760 in modulator output mode enables the output of data directly from the Σ-Δ modulator. This mode of operation bypasses the AD7760 on-board digital filtering capabilities, outputting data in its unfiltered form. As discussed ...

Page 20

AD7760 MODULATOR DATA OUTPUT MODE INTERFACE The AD7760 can be configured in modulator data output mode (bypassing the default decimation filtering) by writing 0 to each of the bits contained in Control Register 1: BYP F1 , BYP F3 , ...

Page 21

DRDY D[0:15] MCLK t 11 CS, RD/WR In the case where odd number of MCLK cycles, the modulator data output on Pins D [15:0] is output on the rising edge of DRDY . In this case, the ...

Page 22

AD7760 AD7760 INTERFACE READING DATA When the AD7760 is outputting data MHz output data rate or less, the interface operates in a conventional mode, as shown in Figure 2, using a 16-bit bidirectional parallel interface. This interface ...

Page 23

WRITING TO THE AD7760 There are many features and parameters that the user can change by writing to the AD7760 device. See the Using the AD7760 section, which details the writing sequence needed to initialize the operation of the part. ...

Page 24

AD7760 CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source. This signal is applied to the MCLK pin, and the MCLKGND pin is used to sense the ground from the clock source. An internal clock signal (ICLK) ...

Page 25

Figure 48. Maximum Slew Rate of Sine Wave with Amplitude p-p 1.0 0.5 0 –0.5 –1.0 Figure 49. Maximum Slew Rate of Sine Wave (with the Same Frequency as in Figure 48) ...

Page 26

AD7760 DRIVING THE AD7760 The AD7760 has an on-chip differential amplifier that operates with a supply voltage (AV 3) within the 3. 5.25 V range. DD For a 4.096 V reference, the supply voltage must ...

Page 27

To obtain maximum performance from the AD7760 advisable to drive the ADC with differential signals. Figure 53 shows how a bipolar, single-ended signal biased around ground can drive the AD7760 with the use of an external op amp, ...

Page 28

AD7760 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7760, correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet. Figure 55 shows a simplified connection diagram for the ...

Page 29

SUPPLY DECOUPLING Every supply pin must be connected to the appropriate supply via a ferrite bead and decoupled to the correct ground pin with a 100 nF, 0603 case size, X7R dielectric capacitor. There are two exceptions to this: • ...

Page 30

AD7760 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7760 is user programmable. The default coefficients that are loaded upon reset are given in Table 10, and the frequency responses are shown in Figure 57. The ...

Page 31

DOWNLOADING A USER-DEFINED FILTER As previously mentioned, the filter coefficients are 27 bits in length—one sign and 26 magnitude bits. Because the AD7760 has a 16-bit parallel bus, the coefficients are padded with 5 MSB 0s to generate a 32-bit ...

Page 32

AD7760 Table 13 shows the hexadecimal values (in sign-and-magnitude format) that are downloaded to the AD7760 to realize this filter. The table is also split into the bytes that are summed to produce the checksum. The checksum generated from these ...

Page 33

AD7760 REGISTERS The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing ...

Page 34

AD7760 STATUS REGISTER (READ ONLY) MSB D15 D14 D13 D12 D11 PART 1 PART 0 DIE 2 DIE 1 DIE 0 Table 17. Bit Descriptions of Status Register Bit Mnemonic Comment 15, 14 PART [1:0] Part Number. These bits are ...

Page 35

... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 AD7760BSVZ −40°C to +85°C 1 AD7760BSVZ-REEL −40°C to +85°C EVAL-AD7760EB Pb-free part. 12.20 12.00 SQ 1.20 11.80 MAX PIN 1 TOP VIEW (PINS DOWN) ...

Page 36

AD7760 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04975-0-8/06(A) Rev Page ...

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