KAD5512P-25Q72 Intersil, KAD5512P-25Q72 Datasheet - Page 20

• Manufacturer Part Number: KAD5512P-25Q72
• Description: IC ADC 12BIT 250MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-25Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 286mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This dual transformer scheme is used to improve common-
mode rejection, which keeps the common-mode level of
the input matched to VCM. The value of the shunt resistor
should be determined based on the desired load
impedance. The differential input resistance of the
KAD5512P is 1000Ω.
The SHA design uses a switched capacitor input stage
(see Figure 43), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
A differential amplifier, as shown in Figure 30, can be
used in applications that require DC-coupling. In this
configuration, the amplifier will typically dominate the
achievable SNR and distortion performance.
The current spikes from the SHA will try to force the
analog input pins toward ground. In cases where the
input pins are biased with more than 50Ω in series from
VCM care must be taken to make sure the input common
mode range is not violated. The provided ICM value
(250µA/MHz * 250MHz = 625µA at 250MSPS) may be
FIGURE 28. TRANSFORMER INPUT FOR GENERAL
FIGURE 29. TRANSMISSION-LINE TRANSFORMER
1000pF
49.9
0.22µF
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
1000pF
1000pF
Ω
ADT1-1WT
69.8
69.8
ADTL1-12
PURPOSE APPLICATIONS
INPUT FOR HIGH IF APPLICATIONS
Ω
100
100
Ω
Ω
Ω
ADTL1-12
ADT1-1WT
348
348
20
CM
Ω
Ω
0.1µF
0.1µF
25
25
0.1µF
Ω
Ω
217
Ω
VCM
KAD5512P
KAD5512P
KAD5512P
VCM
VCM
KAD5512P
used to calculate the expected voltage drop across any
series resistance.
VCM Output
The VCM output is buffered with a series output
impedance of 20Ω. It can easily drive a typical ADC
driver’s 10kΩ common mode control pin. If an external
buffer is not used the voltage drop across the internal
20Ω impedance must be considered when calculating the
expected DC bias voltage at the analog input pins.
Clock Input
The clock input circuit is a differential pair (see
Figure 44). Driving these inputs with a high level (up to
1.8V
the lowest jitter performance. A transformer with 4:1
impedance ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 31. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge rate
and may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC coupling.
A selectable 2x frequency divider is provided in series
with the clock input. The divider can be used in the 2x
mode with a sample clock equal to twice the desired
sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple ADCs.
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 24.
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL may
take up to 52µs to regain lock at 250MSPS. The lock time
is inversely proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts
the achievable SNR performance. The theoretical
relationship between clock jitter (t
Equation 1 and is illustrated in Figure 32.
PP
200pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
on each input) sine or square wave will provide
CLKDIV PIN
AVDD
TABLE 1. CLKDIV PIN SETTINGS
AVSS
Float
TC4-1W
1000pF
J
) and SNR is shown in
DIVIDE RATIO
200pF
200pF
200O
2
1
4
Ω
October 1, 2010
FN6807.4
CLKP
CLKN