KAD5512P-25Q72 Intersil, KAD5512P-25Q72 Datasheet - Page 22

• Manufacturer Part Number: KAD5512P-25Q72
• Description: IC ADC 12BIT 250MSPS SGL 72-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-25Q72

• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 286mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN Exposed Pad
• For Use With: KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In an application where CSB was kept low in sleep
mode, the 150µs CSB setup time is not required as the
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up time after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional
SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a
high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. Recovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52µs to regain lock
at 250MSPS.
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial Peripheral
Interface” on page 24. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format
is selected via the OUTFMT pin as shown in Table 4.
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 24.
–Full Scale + 1LSB
+Full Scale – 1LSB
INPUT VOLTAGE
+Full Scale
–Full Scale
Mid–Scale
OUTFMT PIN
NAPSLP PIN
TABLE 4. OUTFMT PIN SETTINGS
AVDD
AVDD
TABLE 3. NAPSLP PIN SETTINGS
AVSS
AVSS
Float
Float
22
OFFSET BINARY
000 00 000 00 00
000 00 000 00 01
100 00 000 00 00
111 11 111 11 10
111 11 111 11 11
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
Two’s Complement
Offset Binary
Gray Code
Normal
MODE
MODE
Sleep
Nap
KAD5512P
TWO’S COMPLEMENT
Offset binary coding maps the most negative input voltage
to code 0x000 (all zeros) and the most positive input to
0xFFF (all ones). Two’s complement coding simply
complements the MSB of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 33
shows this operation.
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 34.
Mapping of the input voltage to the various data formats
is shown in Table 5.
100 00 000 00 00
100 00 000 00 01
000 00 000 00 00
011 11 111 11 10
011 11 111 111 1
FIGURE 33. BINARY TO GRAY CODE CONVERSION
FIGURE 34. GRAY CODE TO BINARY CONVERSION
GRAY CODE
GRAY CODE
BINARY
BINARY
11
11
11
11
10
10
10
10
9
9
9
9
000 00 000 00 00
110 00 000 00 00
100 00 000 00 00
000 00 000 00 01
100 00 000 00 01
GRAY CODE
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