KAD5514P-25Q48 Intersil, KAD5514P-25Q48 Datasheet - Page 20

• Manufacturer Part Number: KAD5514P-25Q48
• Description: IC ADC 14BIT 250MSPS SGL 48-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5514P-25Q48

• Number Of Bits: 14
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 463mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• For Use With: KDC5514-Q48EVAL - DAUGHTER CARD FOR KAD5514KDC5514EVALZ - DAUGHTER CARD FOR KAD5514
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on this
are contained in “Serial Peripheral Interface” on page 22.
A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52µs to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The
slow range can be used for sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t
is illustrated in Figure 32.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
SNR
100
95
90
85
80
75
70
65
60
55
50
1M
=
20 log
CLKDIV PIN
AVSS
AVDD
Float
FIGURE 32. SNR vs CLOCK JITTER
tj = 100ps
10
TABLE 1. CLKDIV PIN SETTINGS
⎛
⎝
------------------- -
2πf
1
IN
J
INPUT FREQUENCY (Hz)
t
) and SNR is shown in Equation 1 and
10M
J
⎞
⎠
tj = 10ps
20
tj = 1ps
tj = 0.1ps
DIVIDE RATIO
100M
2
1
4
10 BITS
14 BITS
12 BITS
(EQ. 1)
1G
KAD5514P
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or single
data rate (SDR) formats. The even numbered data output
pins are active in DDR mode in the 72 pin package option.
When CLKOUT is low the MSB and all odd logical bits are
output, while on the high phase the LSB and all even logical
bits are presented (this is true in both the 72 pin and 48 pin
package options). Figures 1 and 2 on page page 7show the
timing relationships for LVDS/CMOS and DDR/SDR modes.
The 48 Ld QFN package option contains seven LVDS data
output pin pairs, and therefore can only support DDR mode.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in the “Serial Peripheral Interface” on
page 22.
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode).
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5514P is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
OUTMODE PIN
AVDD
AVSS
Float
TABLE 2. OUTMODE PIN SETTINGS
LVDS, 3mA
LVDS, 2mA
LVCMOS
MODE
September 10, 2009
FN6804.2