ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 37

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC083000 may be operated in the non-extended con-
trol (non-Serial Interface) mode or in the extended control
mode. Table 8 and Table 9 describe the functions of pins 3,
4, 14 and 127 in the non-extended control mode and the ex-
tended control mode, respectively.
2.9.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. That is, the output voltage,
full-scale range and output edge selections are all controlled
with pin settings. The non-extended control mode is used by
setting pin 14 high or low, as opposed to letting it float. Table
8 indicates the pin functions of the ADC083000 in the non-
extended control mode.
TABLE 8. Non-Extended Control Mode Operation (Pin 14
Pin 3 can be either high or low in the non-extended control
mode. Pin 14 must not be left floating to select this mode. See
Section 1.2 for more information.
Pin 4 can be high or low or can be left floating in the non-
extended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See Section 1.2 for more information. If this pin is
floating, the output clock (DCLK) is a DDR (Double Data Rate)
clock (see Section 1.1.5.3) and the output edge synchroniza-
tion is irrelevant since data is clocked out on both DCLK
edges.
Pin 127, if it is high or low in the non-extended control mode,
sets the calibration delay. If pin 127 is floating, the calibration
delay is the same as it would be with this pin low and this pin
acts as the enable pin for the serial interface input.
TABLE 9. Extended Control Mode Operation (Pin 14
127
Pin
14
3
4
127
Pin
3
4
input range
CalDly Low
OutEdge =
600 mV
0.52 V
Output
Low
Neg
SCS (Serial Interface Chip Select)
High or Low)
P-P
P-P
Floating)
SDATA (Serial Data)
SCLK (Serial Clock)
CalDly High
input range
OutEdge =
820 mV
0.68 V
Output
Function
High
Pos
P-P
P-P
Control Mode
Extended
Floating
Interface
Enable
Serial
DDR
n/a
37
2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all six
address locations must be written at least once with the de-
fault or desired values before calibration and subsequent use
of the ADC.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the
ADC083000. Such practice may lead to conversion inaccu-
racies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in section 1.1.4 and 2.2, the
Input common mode voltage must remain within 50 mV of the
V
must also be tracked. Distortion performance will be degrad-
ed if the input common mode voltage is more than 50 mV from
V
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC083000 as many high speed amplifiers will have
higher distortion than will the ADC083000, resulting in overall
system performance degradation.
Driving the V
mentioned in Section 2.1, the reference voltage is intended to
be fixed to provide one of two different full-scale values (600
mV
the full scale value, but can be used to change the LVDS
common mode voltage from 0.8V to 1.2V by tying the V
to V
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels. As described in Section 2.3,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction of
an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in
Section 2.6.2, it is important to provide adequate heat removal
to ensure device reliability. This can be done either with ad-
equate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-
mance.
CMO
CMO
P-P
A
.
.
output , which has a variability with temperature that
and 820 mV
BG
pin to change the reference voltage. As
P-P
). Over driving this pin will not change
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BG
pin