LTC2442IG#PBF Linear Technology, LTC2442IG#PBF Datasheet - Page 18

• Manufacturer Part Number: LTC2442IG#PBF
• Description: IC ADC 24BIT 4CH 36-SSOP
• Manufacturer: Linear Technology

Specifications of LTC2442IG#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 8k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC2442
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
6. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. Conversely, BUSY (Pin 2) may
be used to monitor the status of the conversion cycle.
EOC or BUSY may be used as an interrupt to an external
18
(EXTERNAL)
BUSY
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
U
SLEEP
U
1
BIT 31
EOC
1
2
Figure 6. External Serial Clock, CS = 0 Operation (2-Wire)
BIT 30
0.1V TO V
REFERENCE
“0”
W
ANALOG
0
INPUTS
VOLTAGE
0.1µF
0.1µF
1µF
3
4.5V TO 5.5V
BIT 29
SIG
EN
CC
4
29
30
31
28
12
13
11
17
18
10
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
MSB
6
7
8
9
SGL
V
REF
REF
CH0
CH1
CH2
CH3
COM
OUTA
–INA
ADCINA
OUTB
–INB
ADCINB
CC
U
5
+
–
LTC2442
ODD
MUXOUTA
MUXOUTB
6
BUSY
+INA
+INB
SDO
GND
SCK
0
EXT
SDI
CS
V
F
V
+
O
–
7
V
21
27
25
26
19
24
4, 5, 32
CC
0
33
36
35
34
3
1
2
TO 15V
DATA OUTPUT
controller indicating the conversion result is ready. EOC =
1 (BUSY = 1) while the conversion is in progress and EOC
= 0 (BUSY = 0) once the conversion enters the sleep state.
On the falling edge of EOC/BUSY, the conversion result
is loaded into an internal static shift register. The device
remains in the sleep state until the fi rst rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the fi rst rising edge of SCK.
On the 32nd falling edge of SCK, SDO and BUSY go HIGH
(EOC = 1) indicating a new conversion has begun.
–15V TO GND
8
1µF
A0
3-WIRE
SPI INTERFACE
9
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
OSR3
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
10
OSR2
11
OSR1
12
OSR0 TWOX
13
14
DON'T CARE
BIT 0
32
LSB
2442 F06
CONVERSION
2442f