ADC101C021CIMKX/NOPB National Semiconductor, ADC101C021CIMKX/NOPB Datasheet
ADC101C021CIMKX/NOPB
Specifications of ADC101C021CIMKX/NOPB
Related parts for ADC101C021CIMKX/NOPB
ADC101C021CIMKX/NOPB Summary of contents
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... ADCs that also provide 12 and 8 bit resolution. For 12-bit ADCs see the ADC121C021 and ADC121C027. For 8-bit ADCs see the ADC081C021 and ADC081C027. Connection Diagrams 30052001 I2C® registered trademark of Phillips Corporation. © 2009 National Semiconductor Corporation ADC101C021/ADC101C027 Features ■ C-Compatible 2-wire Interface which supports standard (100kHz), fast (400kHz), and high speed (3 ...
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Ordering Information Order Code ADC101C021CIMK ADC101C021CIMKX ADC101C027CIMK ADC101C027CIMKX ADC101C021CIMM ADC101C021CIMMX ADC101C021EB Block Diagram www.national.com Option Alert pin Alert pin TSOT-6 Tape-and-Reel Address pin Address pin TSOT-6 Tape-and-Reel Alert and Address pins Alert and Address pins Shipped with the ADC101C021 (TSOT-6). ...
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Pin Descriptions Symbol Type V Supply A GND Ground V Analog Input IN ALERT Digital Output SCL Digital Input Digital SDA Input/Output ADR0 Digital Input, three levels ADR1 Package Pinouts V A ADC101C021 1 TSOT-6 ADC101C027 1 TSOT-6 ADC101C021 5 ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Voltage on any Analog Input Pin to GND Voltage on any Digital Input Pin to GND Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation 25° ...
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Symbol Parameter SFDR Spurious-Free Dynamic Range Intermodulation Distortion, Second Order Terms (IMD ) 2 IMD Intermodulation Distortion, Third Order Terms (IMD ) 3 FPBW Full Power Bandwidth (−3dB) ANALOG INPUT CHARACTERISTICS V Input Range Leakage Current (Note ...
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Symbol Parameter POWER REQUIREMENTS Supply Voltage Minimum V A Supply Voltage Maximum Continuous Operation Mode -- 2-wire interface active. I Supply Current N P Power Consumption N Automatic Conversion Mode -- 2-wire interface stopped and quiet (SCL = SDA = ...
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A.C. and Timing Characteristics The following specifications apply for 25°C, unless otherwise specified. A Symbol Parameter CONVERSION RATE Conversion Time f Conversion Rate CONV DIGITAL TIMING SPECS (SCL, SDA) f Serial Clock Frequency SCL t SCL Low ...
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Symbol Parameter t Rise time of SDA signal rDA t Fall time of SDA signal fDA t Rise time of SCL signal rCL Rise time of SCL signal after a t repeated start condition and after an rCL1 acknowledge bit. ...
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Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of V example 3V, the digital input pins can be driven with a 5V logic device. A Note 8: To guarantee ...
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Specification Definitions ACQUISITION TIME is the time required for the ADC to ac- quire the input voltage. During this time, the hold capacitor is charged by the input voltage. APERTURE DELAY is the time between the start of a con- ...
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Typical Performance Characteristics +25°C, unless otherwise stated. INL vs. Code - V A INL vs. Code - V A INL vs. Supply f = 400kHz, f SCL =3V 30052022 =5V 30052024 30052026 11 = 22kSPS 1kHz ...
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ENOB vs. Supply FFT Plot - V Offset Error vs. Temperature www.national.com 30052028 =3V A 30052030 30052032 12 SINAD vs. Supply 30052029 FFT Plot - V =3V A 30052031 Gain Error vs. Temperature 30052033 ...
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Continuous Operation Supply Current vs. V Power Down (PD ) Supply Current vs Automatic Conversion Supply Current vs 30052034 A 30052036 13 A 30052035 www.national.com ...
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Functional Description The ADC101C021 is a successive-approximation analog-to- digital converter designed around a charge-redistribution dig- ital-to-analog converter. Unless otherwise stated, references to the ADC101C021 in this section will apply to both the ADC101C021 and the ADC101C027. 1.1 CONVERTER OPERATION ...
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REFERENCE VOLTAGE The ADC101C021 uses the supply ( the reference must be treated as a reference. The analog-to-digital con- A version will only be as precise as the reference (V supply voltage should be ...
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Address Pointer Register The address pointer determines which of the data registers is accessed by the interface. The first data byte of every write operation is stored in the address pointer register. This value selects the ...
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Conversion Result Register This register holds the result of the most recent conversion. In the normal mode, a new conversion is started whenever this register is read. The conversion result data is in straight binary format with the MSB ...
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Configuration Register Pointer Address 02h (Read/Write) Default Value: 00h Cycle Time [2:0] Alert Alert Hold Flag Enable Cycle Time[2:0] Conversion Interval Mode Disabled Bits Name Description 7:5 Cycle ...
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V -- Alert Limit Register - Over Range HIGH This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher than this limit alert is generated. HIGH Pointer Address 04h ...
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D7 D6 Bits Name Description 15:12 Reserved Always reads zeros. Zeros must be written to these bits. 11:2 Lowest Conversion Contains the Lowest Conversion result. D11 is MSB. 1:0 Reserved Always reads zeros. Zeros must be written to these bits. ...
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Please refer to the Philips ® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial interface. 1.7.2 Standard-Fast Mode In Standard-Fast mode, the master generates a start condi- tion by driving SDA from high ...
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Slave (Hardware) Address The ADC has a seven-bit hardware address which is also re- ferred slave address. For the MSOP-8 version of the ADC101C021, this address is configured by the ADR0 and ADR1 ...
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Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the alert condition persists and only clears when a one is written to the Under Range Alert Flag bit. If the alert condition has ...
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FIGURE 11. (a) Typical Read from a 2-Byte ADC Register with Preset Pointer FIGURE 12. (b) Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register 1.10.2 Reading from a 1-Byte ADC Register The following diagrams indicate the ...
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FIGURE 14. (b) Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register 1.10.3 Writing to an ADC Register The following diagrams indicate the sequence of actions re- quired for writing to an ADC101C021 Register. FIGURE 15. (a) ...
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FIGURE 16. (b) Typical Write to a 2-Byte ADC Register 1.11 QUIET INTERFACE MODE To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved INL and DNL performance Hs-Mode ...
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... BUFFERED INPUT A buffered input application circuit is shown in Figure 19. The analog input is buffered by a National Semiconductor LMP7731. The non-inverting amplifier configuration provides a buffered gain stage for a single ended source. This appli- cation circuit is good for single-ended sensor interface ...
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INTELLIGENT BATTERY MONITOR The ADC101C021 is easily used as an intelligent battery monitor. The simple circuit shown in Figure 20, uses the ADC101C021, the LP2980 fixed reference, and a resistor di- vider to implement an intelligent battery monitor with ...
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Physical Dimensions inches (millimeters) unless otherwise noted Order Numbers ADC101C021CIMK & ADC101C027CIMK 6-Lead TSOT NS Package Number MK06A 8-Lead MSOP Order Numbers ADC101C021CIMM NS Package Number MUA08A 29 www.national.com ...
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