KAD5512P-12Q48 Intersil, KAD5512P-12Q48 Datasheet - Page 26

• Manufacturer Part Number: KAD5512P-12Q48
• Description: IC ADC 12BIT 125MSPS SGL 48-QFN
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KAD5512P-12Q48

• Number Of Bits: 12
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 235mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• For Use With: KDC5512-Q48EVAL - DAUGHTER CARD FOR KAD5512KDC5512EVAL - DAUGHTER CARD FOR KAD5512
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 21). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
Nap mode must be entered by executing the following
sequence:
Return to Normal operation as follows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple ADCs are used in a time-interleaved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 41. Execution
of a phase_slip command is accomplished by first writing
a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit
0 at address 71h (32 sclk cycles).
SEQUENCE
SEQUENCE
1
2
3
4
1
2
3
4
TABLE 10. POWER-DOWN CONTROL
VALUE
000
001
010
100
REGISTER
REGISTER
26
0x10
0x25
0x10
0x25
0x10
0x25
0x10
0x25
POWER-DOWN MODE
Normal Operation
Sleep Mode
0x25[2:0]
Pin Control
Nap Mode
VALUE
VALUE
0x01
0x02
0x02
0x02
0x01
0x01
0x02
0x01
KAD5512P
SLIP TWICE
FIGURE 41. PHASE SLIP: CLK÷4 MODE, f
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default,
the tri-level CLKDIV pin selects the divisor (refer to “VCM
Output” on page 20). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 21). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 22). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
SLIP ONCE
CLK÷4
CLK÷4
CLK÷4
CLK
TABLE 11. CLOCK DIVIDER SELECTION
TABLE 12. OUTPUT MODE CONTROL
VALUE
VALUE
1000MHz
000
001
010
100
000
001
010
100
CLK = CLKP – CLKN
1.00ns
CLOCK DIVIDER
4.00ns
0x72[2:0]
Divide by 1
Divide by 2
Divide by 4
Pin Control
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
CLOCK
October 1, 2010
=
FN6807.4