MAX5478EUD+ Maxim Integrated Products, MAX5478EUD+ Datasheet - Page 12

• Manufacturer Part Number: MAX5478EUD+
• Description: IC POT DGTL DUAL 256-TAP 14TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5478EUD+

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 325 Ohms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Supply Current: 1 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Description/function: Dual, 256 Tap, Nonvolatile, I2C, 50k Digital Potentiometer
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 256-Tap, Nonvolatile, I
Digital Potentiometers
register with input shift register data and change the
wiper position. Use valid 3-byte I
proper operation. This precautionary operation is nec-
essary only when transitioning from write protected (WP
= 1) to not write protected (WP = 0).
The MAX5477/MAX5478/MAX5479 operate as slave
devices that send and receive data through an I
SMBus™-compatible 2-wire serial interface. The inter-
face uses a serial data access (SDA) line and a serial
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master, typically a
microcontroller, initiates all data transfers to the
MAX5477/MAX5478/MAX5479, and generates the SCL
clock that synchronizes the data transfer
The MAX5477/MAX5478/MAX5479 SDA line operates
as both an input and an open-drain output. The SDA
line requires a pullup resistor, typically 4.7kΩ. The
MAX5477/MAX5478/MAX5479 SCL line operates only
as an input. The SCL line requires a pullup resistor (typ-
ically 4.7kΩ) if there are multiple masters on the 2-wire
interface, or if the master in a single-master system has
an open-drain SCL output. SCL and SDA should not
exceed V
open-drain drivers.
Each transmission consists of a START (S) condition
(Figure
MAX5477/MAX5478/MAX5479 7-bit slave address plus
the
byte, and finally a STOP (P) condition
Both SCL and SDA remain high when the interface is
not busy. A master controller signals the beginning of a
transmission with a START condition by transitioning
SDA from high to low while SCL is high. The master
controller issues a STOP condition by transitioning the
SDA from low to high while SCL is high, when it finishes
Figure 4. Slave Address
SMBus is a trademark of Intel Corporation.
12
NOP/W bit
SDA
SCL
______________________________________________________________________________________
START
3) sent by a master, followed by the
DD
in a mixed-voltage system, despite the
(Figure
MSB
0
4), 1 command byte and 1 data
Start and Stop Conditions
1
Serial Addressing
2
C commands for
(Figure
(Figure
0
3).
1).
2
C-/
1
communicating with the slave. The bus is then free for
another transmission
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data
6). Thus, each byte transferred effectively requires 9 bits.
The master controller generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line remains stable low during
the high period of the clock pulse.
The MAX5477/MAX5478/MAX5479 have a 7-bit-long
slave address
slave address is the NOP/W bit. Set the NOP/W bit low for
a write command and high for a no-operation command.
The MAX5477/MAX5478/MAX5479 provide three
address inputs (A0, A1, and A2), allowing up to eight
devices to share a common bus
bits (MSBs) of the MAX5477/MAX5478/MAX5479 slave
addresses are always 0101. A2, A1, and A0 set the next
Figure 3. Start and Stop Conditions
SDA
SCL
A2
CONDITION
START
(Figure
S
2
C-Interface,
A1
5).
(Figure
(Figure
LSB
A0
4). The 8th bit following the 7-bit
3).
NOP/W
(Table
Slave Address
Acknowledge
1). The first 4
ACK
Bit Transfer
CONDITION
(Figure
STOP
P