X9111TV14IZ-2.7T1 Intersil, X9111TV14IZ-2.7T1 Datasheet

IC POT DGTL 100K OHM 14-TSSOP

X9111TV14IZ-2.7T1

Manufacturer Part Number
X9111TV14IZ-2.7T1
Description
IC POT DGTL 100K OHM 14-TSSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of X9111TV14IZ-2.7T1

Taps
1024
Resistance (ohms)
100K
Number Of Circuits
1
Temperature Coefficient
300 ppm/°C Typical
Memory Type
Non-Volatile
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Resistance In Ohms
100K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
X9111TV14IZ-2.7T1TR
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9111 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Functional Diagram
Interface
SPI
Bus
®
Address
Status
Data
1
Data Sheet
Interface &
Control
V
Bus
V
SS
CC
XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
Transfer
1-888-INTERSIL or 1-888-468-3774
Control
Write
Read
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Single Supply/Low Power/1024-Tap/SPI Bus
Power On Recall
Register (WCR)
Data Registers
Features
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for Write, Read, And Transfer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
• Standby Current <3µA Max
• V
• 100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9110
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
Wiper Counter
NC
September 15, 2006
(DR0-DR3)
Operations Of The Potentiometer
Power-Up.
CC
: 2.7V to 5.5V Operation
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
SCK
V
SO
NC
CS
A0
SS
SI
R
W
Wiper
1
2
3
4
5
6
7
TSSOP
X9111
R
R
H
L
POT
100kΩ
1024-taps
14
13
12
11
10
9
8
V
R
R
R
HOLD
A1
WP
CC
L
H
W
FN8159.4
X9111

Related parts for X9111TV14IZ-2.7T1

X9111TV14IZ-2.7T1 Summary of contents

Page 1

... Register (WCR) Interface & Control Data Registers (DR0-DR3) Control CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X9111 FN8159.4 TSSOP ...

Page 2

... X9111TV14Z-2.7 (Note) X9111TV ZF X9111TV14I-2.7* X9111TV G X9111TV14IZ-2.7* (Note) X9111TV ZG *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...

Page 3

... The V pin is the system supply voltage. The V CC the system ground. Other Pins NO CONNECT (NC) Pin should be left open. This pin is used for Intersil manufacturing and test purposes. Principles of Operation Device Description Serial Interface The X9111 supports the SPI interface hardware conventions. ...

Page 4

Serial Data Path From Interface Circuitry Register 0 (DR0) Register 2 (DR2) If WCR = 000[HEX] then WCR = 3FF[HEX] then FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM These switches ...

Page 5

X9111 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A1–A0 inputs can be actively driven by CMOS input ...

Page 6

Five of the seven instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – read the current wiper position of the selected pot, • Write Wiper Counter Register – change current wiper position of the ...

Page 7

CS SCK R/W I2 ID3 ID2 ID1 ID0 0 A1 Internal Device ID Address FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS) INSTRUCTION R/W Read Wiper Counter 1 Register Write Wiper Counter ...

Page 8

Read Data Register (DR) Device Device Type Addresses Identifier CS Falling Edge Write Data Register (DR) Device Type Device Identifier Addresses CS Falling Edge Transfer ...

Page 9

Absolute Maximum Ratings Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . ...

Page 10

D.C. Operating Characteristics Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER I V supply current CC1 CC (active supply current CC2 CC (nonvolatile write current (standby Input leakage current LI I ...

Page 11

Equivalent A.C. Load Circuit 5V 1462Ω SO pin 2714Ω 100pF AC Timing SYMBOL f SSI/SPI clock frequency SCK t SSI/SPI clock cycle time CYC t SSI/SPI clock high time WH t SSI/SPI clock low time WL t Lead time LEAD ...

Page 12

High-voltage Write Cycle Timing SYMBOL t High-voltage write cycle time (store instructions) WR XDCP Timing SYMBOL t Wiper response time after the third (last) power supply is stable WRPO t Wiper response time after instruction issued (all load instructions) WRL ...

Page 13

Timing Diagrams Input Timing CS t LEAD SCK MSB SI High Impedance SO Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD 13 X9111 t CYC ...

Page 14

XDCP Timing (for All Load Instructions) CS SCK MSB High Impedance SO Write Protect and Device Address Pins Timing Applications information Basic Configurations of Electronic Potentiometers V R Three terminal Potentiometer; Variable voltage ...

Page 15

Application Circuits Noninverting Amplifier – (1 Offset Voltage Adjustment 100kΩ – + TL072 10kΩ 10kΩ 10kΩ +12V -12V 15 X9111 V V ...

Page 16

Application Circuits (Continued) Attenuator – -1/2 ≤ G ≤ +1/2 Inverting Amplifier ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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