X9400WV24I-2.7T1 Intersil, X9400WV24I-2.7T1 Datasheet - Page 5

• Manufacturer Part Number: X9400WV24I-2.7T1
• Description: IC XDCP QUAD 64-TAP 10K 24-TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9400WV24I-2.7T1

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 1. Detailed Potentiometer Block Diagram
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9400 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
pins. The X9400 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9400 to successfully
If WCR = 00[H] then V
If WCR = 3F[H] then V
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
W
W
/R
/R
W
W
= V
= V
5
Register 0
Register 2
L
H
/R
/R
L
H
8
0
- A
1
Register 1
Register 3
input
Modified SCL
X9400
UP/DN
6
continue the command sequence. The A
can be actively driven by CMOS input signals or tied to
V
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
CC
Parallel
Bus
Input
UP/DN
CLK
Serial
Bus
Input
or V
Register
Counter
INC/DEC
SS
(WCR)
0
Wiper
Logic
.
Device Type
Identifier
1
0
C
o
u
n
e
D
e
c
o
d
e
t
r
1
0
0
Device Address
A1
0
- A
A0
V
V
V
H
L
W
July 28, 2006
/R
1
/R
/R
H
FN8189.3
L
inputs
W