IP4786CZ32 NXP Semiconductors, IP4786CZ32 Datasheet
IP4786CZ32
Specifications of IP4786CZ32
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IP4786CZ32 Summary of contents
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... ElectroStatic Discharge (ESD) protection for all I/Os in accordance with the IEC 61000-4-2, level 4 standard. The IP4786CZ32 incorporates Transmission Line Clamping (TLC) technology on the high-speed Transition Minimized Differential Signaling (TMDS) lines to simplify routing and help reduce impedance discontinuities. All TMDS lines are protected by an impedance-matched diode configuration that minimizes impedance discontinuities caused by typical shunt diodes ...
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... Simplified flow-through routing utilizing less overall PCB space Highest integration in a small footprint, PCB level, optimized RF routing, 32-pin HVQFN leadless package 3. Applications The IP4786CZ32 can be used for a wide range of HDMI source devices, consumer and computing electronics: Standard-Definition (SD) and High-Definition (HD) DVD player Set-top box ...
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... ESD HOTPLUG_DET_SYS 100 kΩ ESD V CC(5V0 ESD V CC(SYS Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 ESD CC(5V0) 3.3 V VOLTAGE ESD REGULATOR CEC driver 26 kΩ HDMI_5V0_CON ESD DDC driver 1.85 kΩ HDMI_5V0_CON DDC driver ESD 1.85 kΩ ...
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... TMDS_D2+_SYS 2 TMDS_D2–_SYS TMDS_D1+_SYS 3 TMDS_D1–_SYS 4 TMDS_D0+_SYS 5 6 TMDS_D0–_SYS 7 TMDS_CK+_SYS TMDS_CK–_SYS 8 Transparent top view Pin configuration IP4786CZ32 Pin description Name TMDS_D2+_SYS TMDS_D2−_SYS TMDS_D1+_SYS TMDS_D1−_SYS TMDS_D0+_SYS TMDS_D0−_SYS TMDS_CK+_SYS TMDS_CK−_SYS DDC_CLK_SYS DDC_DAT_SYS V CC(5V0) HOTPLUG_DET_CON HDMI_5V0_CON All information provided in this document is subject to legal disclaimers. ...
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... CEC_SYS n.c. n.c. HOTPLUG_DET_SYS GND All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Description DDC data connector side DDC clock connector side utility line ESD protection TMDS ESD protection to connector TMDS ESD protection to connector TMDS ESD protection to connector ...
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... DDC and CEC bus in idle mode; CEC_STBY = HIGH; no current at HDMI_5V0_CON DDC and CEC bus in idle mode; CEC_STBY = LOW All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Min Max Unit GND − 0.5 6.5 V GND − 0.5 5.5 V ± ...
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... NXP Semiconductors 8. Static characteristics Table 4. − amb Symbol V CC(5V0) V CC(SYS) [1] The IP4786CZ32 contains voltage regulator function for higher input voltages. Any input voltage of 4.925 V < HDMI_5V0_CON. Table 5. − amb Symbol TMDS channel Z i(dif) C eff Protection diode V BRzd r dyn I bck CL(ch)trt(pos) [1] This parameter is guaranteed by design. ...
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... Symbol r dyn O(max) I bck I O(sc O(LDO) [1] ANSI-ESDSP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR. [2] The IP4786CZ32 contains voltage regulator function for higher input voltages. Any input voltage of 4.925 V < HDMI_5V0_CON Table 7. − amb Symbol Supplies: pins V r dyn [1] ANSI-ESDSP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR. ...
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... CC(SYS 5 CC(SYS) = − [2] V CC(SYS) [ CC(5V0 CC(SYS 2.5 V; bias AC input = 3 (p- 100 kHz 3.2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Typ Max - 6.5 0.3 × (HDMI_5V0_CON) 100 200 −1 (HDMI_5V0_CON) + 0.02 8.0 10 1.8 2 330 ...
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... V; bias AC input = 3 (p- 100 kHz [ CC(5V0 CC(SYS 2.5 V; bias AC input = 3 (p- 100 kHz All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Min Typ Max 2 0.80 2.88 3.3 3.63 - 100 200 - 8.0 10 23.4 26.0 28.6 450 ...
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... Conditions = − 4 6.5 V; GND = amb Conditions [1] HIGH = active LOW = standby CC(5V0) CC(SYS) All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Min Typ Max 0.7 × CC(SYS) - 200 300 60 100 140 − ° ° +85 C unless otherwise specified. ...
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... Figure 18 connector side Figure 18 system side Figure 19 system side Figure 19 018aaa084 Z dif (Ω) 41.8 42.0 t (ns) Fig 4. All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 C unless otherwise specified. Min [1] Figure 16 - Figure 16 - Figure 17 - Figure 120 80 ...
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... Mixed-mode differential and common-mode insertion loss; typical values 3 –3 –9 – normalized to 100 Ω; differential pairs CH1/CH2 versus CH3/CH4 Mixed-mode differential and common-mode NEXT / FEXT; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 018aaa086 (1) ( (Hz) 018aaa087 (1) (2) 8 ...
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... V bias All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 1080p, 225 MHz pixel clock Eye diagram using IP4786CZ32 018aaa090 5.0 7.0 V (V) bias © NXP B.V. 2011. All rights reserved. 018aaa089 ...
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... V (V) CL Fig 13. Dynamic resistance with negative clamping All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 0.4 0.6 0.8 1.0 = 8/20 μs; negative pulse IEC 61000-4- –12 –8 – 100 ns; TLP; signal pins; typical values p © ...
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... V (V) CC(5V0) (1) V (2) V (3) V (4) V Fig 15. Overcurrent limiter function (HDMI_5V0_CON) All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 6.0 (2) (1) 4.0 2.0 0.0 0.00 0.02 0.04 0.06 0.08 0.10 = 4.5 V CC(5V0) = 5.0 V CC(5V0 ...
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... Product data sheet DVI and HDMI interface ESD and overcurrent protection 0.5 V CC(SYS) 0.5 V (HDMI_5V0_CON) t PHL 0.5 V (HDMI_5V0_CON) 0.5 V CC(SYS) t PHL All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 V CC(SYS) 0.28 V CC(SYS (HDMI_5V0_CON) 0.5 V (HDMI_5V0_CON PLH 018aaa097 ...
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... DDC system side Fig 19. Transition time DDC system side IP4786CZ32 Product data sheet DVI and HDMI interface ESD and overcurrent protection (HDMI_5V0_CON (HDMI_5V0_CON) t PHL PHL All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 V CC(SYS (HDMI_5V0_CON PLH V (HDMI_5V0_CON CC(SYS) ...
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... ESD clamping performance by including the ΔI/Δt reactance of the inductance into the path of the ESD shunt. The IP4786CZ32 utilizes these inherent inductances in series with the transmission line in order to present an effective capacitive load of roughly only 0.7 pF. This TLC structure minimizes the capacitive dip, for ideal signal integrity complicated PCB pre-compensation ...
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... The bidirectional buffers support high-capacitive load on the HDMI cable-side. Various non-compliant but prevalent low-cost cables have been observed with a capacitive load the DDC lines, far exceeding the 700 pF HDMI limit. The IP4786CZ32 can easily decouple this from the weaker ASIC I/O buffers, and drive the rogue cable successfully ...
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... I OL(max) threshold on system (ASIC) side to drive I IH(min) threshold on system (ASIC) side to drive I IL(max) (HDMI) side All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 018aaa106 (1) (2) (3) 3.6 4.6 V (V) CC(SYS) C logic low (less than 0.3 × HDMI_5V0_CON) ...
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... The comparator guarantees a save detection of the 2 V hot plug signal without any glitches or oscillation at the hot plug output. The IP4786CZ32 also provides an additional ESD pin to protect the reserved / HEAC pin along with hot plug detect IEC 61000-4-2, level 4. Fig 24. Hot plug detect circuit 11 ...
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... Typically, the DDC lines and the CEC signals can force significant current back into the powered-down rails as shown in system, and possible damage. The IP4786CZ32 prevents this backdrive condition whenever the I/O voltage is greater than the local supply. Fig 26. Generalized backdrive protection ...
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... A typical 100 mV V guarantee 4 5.3 V over the HDMI connector. The overcurrent / overvoltage feature of the IP4786CZ32 allows the use of wider tolerance input supplies up to 6.5 V while still meeting the 4 5.3 V output limit required by HDMI. This means, for example, a cost-reduced 5.2 V ± even a 5.5 V ± ...
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... Schematic view of application Only a single external component (C ASIC to a complete and compliant HDMI port. The 100 nF ESD bypass capacitor is optional. +4 6.5 V SUPPLY +1. 5.5 V SUPPLY Fig 28. Schematic view of IP4786CZ32 application IP4786CZ32 Product data sheet DVI and HDMI interface ESD and overcurrent protection O CEC_STBY CEC_SYS 11 ...
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... NXP Semiconductors 11.9 Typical application The IP4786CZ32 is designed to simplify routing to the HDMI connector, and ease the incorporation of high-level ESD protection into delicately balanced high-speed TMDS lines. These lines rely on tightly controlled microstrip or stripline transmission lines with minimal impedance discontinuities, which can deteriorate return loss, increase deterministic jitter and generally erode overall link signal integrity ...
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... NXP Semiconductors Fig 30. Application of the IP4786CZ32 showing optimized HDMI type-D connector routing IP4786CZ32 Product data sheet DVI and HDMI interface ESD and overcurrent protection All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 001aan368 © NXP B.V. 2011. All rights reserved. ...
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... 5.1 3.75 5.1 3.75 0.5 3.5 3.5 4.9 3.45 4.9 3.45 References JEDEC JEITA MO-220 All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 detail 0.5 0.1 0.05 0.05 0.1 0.3 European projection SOT617-3 y sot617-3_po Issue date ...
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... Solder bath specifications, including temperature and impurities IP4786CZ32 Product data sheet DVI and HDMI interface ESD and overcurrent protection All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 32. All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 Figure 32) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 peak temperature time 001aac844 © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 15. Revision history Table 13. Revision history Document ID Release date IP4786CZ32 v.1 20110415 IP4786CZ32 Product data sheet DVI and HDMI interface ESD and overcurrent protection Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 © NXP B.V. 2011. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 15 April 2011 IP4786CZ32 © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com IP4786CZ32 All rights reserved. Date of release: 15 April 2011 Document identifier: IP4786CZ32 ...