MT4LSDT3232UDG-8D1 Micron Technology Inc, MT4LSDT3232UDG-8D1 Datasheet

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MT4LSDT3232UDG-8D1

Manufacturer Part Number
MT4LSDT3232UDG-8D1
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT4LSDT3232UDG-8D1

Main Category
DRAM Module
Sub-category
SDRAM
Module Type
100UDIMM
Device Core Size
32b
Organization
32Mx32
Total Density
128MByte
Chip Density
256Mb
Access Time (max)
6ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
274mA
Number Of Elements
4
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
100
Mounting
Socket
Lead Free Status / Rohs Status
Not Compliant
SYNCHRONOUS
DRAM MODULE
Features
• 100-pin, dual in-line memory module (DIMM)
• PC 100- and PC133-compliant
• 16MB (4 Meg x 32) , 32MB (8 Meg x 32), 64MB (16
• Utilizes 125 MHz and 133 MHz SDRAM
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD
• Gold edge contacts
Table 1:
CL = CAS (READ) Latency
Table 2:
09005aef80948ad4
SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN
GRADE
MODULE DENSITY
Refresh Count
Device Banks
Device Configuration
Device Row Addressing
Device Column Addressing
Module Ranks
SPEED
Meg x 32), and 128MB (32 Meg x 32)
components
edge of system clock
be changed every clock cycle
16MB, 32MB, and 64MB modules; 64ms, 4,096-cycle
refresh (15.625µs refresh interval); 128MB modules;
64ms, 8,192-cycle refresh (7.81µs refresh interval)
-75
-10
-8
FREQUENCY
133 MHz
125 MHz
100 MHz
CLOCK
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Timing Parameters
Address Table
CL = 2 CL = 3
ACCESS TIME
5.4ns
6ns
9ns
64Mb (4 Meg x 16)
)
5.4ns
7.5ns
6ns
256 (A0–A7)
4 (BA0–BA1)
4K (A0–A11)
1 (S0#, S2#)
16MB
4K
16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR)
SETUP
TIME
1.5ns
2ns
2ns
HOLD
TIME
0.8ns
1ns
1ns
2 (S0#, S2#, S1#, S3#)
64Mb (4 Meg x 16)
256 (A0–A7)
4 (BA0–BA1)
4K (A0–A11)
1
32MB
4K
MT2LSDT432U – 16MB
MT4LSDT832UD – 32MB
MT4LSDT1632UD – 64MB
MT4LSDT3232UD – 128MB
For the latest data sheet, please refer to the Micron
site:
Options
• Package
• Timing (Cycle Timing)
• PCB
Standard 1.00in. (25.40mm)
100-pin DIMM (standard)
100-pin DIMM (lead-free)
7.5ns (133 MHz)
8ns (125 MHz)
10ns (100 MHz)
Standard 1.00in. (25.40mm)
Figure 1: 100-Pin DIMM (MO–161)
www.micron.com/products/modules
2 (S0#, S2#, S1#, S3#)
128Mb (8 Meg x 16)
100-PIN SDRAM UDIMM
512 (A0–A8)
4 (BA0–BA1)
4K (A0–A11)
64MB
4K
©2004 Micron Technology, Inc. All rights reserved.
256Mb (16 Meg x 16)
2 (S0#, S2#, S1#, S3#)
8K (A0–A12)
512 (A0–A8)
4 (BA0–BA1)
128MB
Marking
8K
-75
-10
-8
G
Y
Web

Related parts for MT4LSDT3232UDG-8D1

MT4LSDT3232UDG-8D1 Summary of contents

Page 1

... SYNCHRONOUS DRAM MODULE Features • 100-pin, dual in-line memory module (DIMM) • PC 100- and PC133-compliant • 16MB (4 Meg x 32) , 32MB (8 Meg x 32), 64MB (16 Meg x 32), and 128MB (32 Meg x 32) • Utilizes 125 MHz and 133 MHz SDRAM components • Single +3.3V power supply • ...

Page 2

... MT4LSDT1632UDY-8__ MT4LSDT1632UDG-10__ MT4LSDT1632UDY-10__ MT4LSDT3232UDG-75__ MT4LSDT3232UDY-75__ MT4LSDT3232UDG-8__ MT4LSDT3232UDY-8__ MT4LSDT3232UDG-10__ MT4LSDT3232UDY-10__ NOTE: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT2LSDT432UG-8B1. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) ...

Page 3

... NC DD DQ15 72 RAS DQMB1 73 CAS# 86 Vss Vss 74 RFU 87 DQMB3 75 CK1 (Not populated for the 16MB module) U4 PIN 73 PIN100 pin SS Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 88 DQ24 89 DQ25 90 DQ26 91 DQ27 ...

Page 4

... Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. – Reserved for Future Use: These pins should be left unconnected. – Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version. – Not connected. 4 ...

Page 5

... CKE0 WE# A0-A11 BA0 BA1 NOTE: 1. All resistor values are 10 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) S0# DQMB0 DQML CS# DQ0 DQ DQ1 DQ ...

Page 6

... Figure 4: Functional Block Diagram – 32MB, 64MB, 128MB A0-A11 (32MB, 64MB) A0-A12 (128MB) NOTE: 1. All resistor values are 10 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at numberguide. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) S1# ...

Page 7

... EEPROM device (DIMM) occur via a standard I using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner ...

Page 8

... M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 128MB module, address A12 (M12) is undefined but should be driven LOW during loading of the mode register. ...

Page 9

Table 7: Burst Definition ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...

Page 10

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ ...

Page 11

Commands Table 9, Commands and DQMB Operation Truth Table provides a general reference of available com- mands. For a more detailed description of commands Table 9: Commands and DQMB Operation Truth Table CKE is HIGH for all commands shown except ...

Page 12

Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...

Page 13

... AUTO REFRESH CURRENT: CKE = HIGH HIGH SELF REFRESH CURRENT: CKE 0. Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode Value calculated reflects all module ranks in this operating condition. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) = +3.3V ± ...

Page 14

... AUTO REFRESH CURRENT: CKE = HIGH HIGH SELF REFRESH CURRENT: CKE 0. Value calculated as one module rank in this operating condition, and all other ranks in Power-Down Mode Value calculated reflects all module ranks in this operating condition. 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) = +3.3V ± ...

Page 15

Table 16: Capacitance – 16MB Note: 2; notes appear on page 18 PARAMETER Input Capacitance: Address and Command Input Capacitance: CKE Input Capacitance: CK Input Capacitance: S# Input Capacitance: DQMB Input/Output Capacitance: DQ Table 17: Capacitance – 32MB, 64MB, and ...

Page 16

Table 18: SDRAM Component AC Electrical Characteristics Notes 11, 31; notes appear on page 18 AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) Address hold time Address setup time CLK high-level width CLK low-level width ...

Page 17

Table 19: AC Functional Characteristics Notes 11, 31; notes appear on page 18 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...

Page 18

... The value of t CKS; clock(s) speci- ules is calculated from t t 33. Leakage number reflects the worst-case leakage WR plus RP; clock(s) possible through the module pin, not what each memory device contributes. 18 100-PIN SDRAM UDIMM t WR. current will decrease or decrease in a pro 133 MHz for -75 100 MHz for -10 ...

Page 19

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure ...

Page 20

Table 20: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 21: EEPROM Operating Modes MODE RW BIT Current Address Read RandomAddressRead Sequential Read Byte ...

Page 21

Table 22: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 22

... DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of SPD Memory Bytes 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of Module Ranks 6 Module Data Width 7 Module Data Width (continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK (CAS Latency = 3) 10 SDRAM Access From Clock, ...

Page 23

... Reserved Bytes 62 SPD Revision 63 Checksum for Bytes 0-62 64 Manufacturer's JEDEC ID Code 65-71 Manufacturer's JEDEC Code (Cont.) 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continuted) 93 Year of Manufacture in BCD 94 Week of Manufacture in BCD 95-98 Module Serial Number 99-127 Manufacturer-Specific Data (RSVD) 09005aef80948ad4 SD2_4C4_8_16_32x32UDG ...

Page 24

... DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of SPD Memory Bytes 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of Module Ranks 6 Module Data Width 7 Module Data Width (continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK (CAS Latency = 3) 10 SDRAM Access From Clock, ...

Page 25

... SPD Revision 63 Checksum For Bytes 0-62 64 Manufacturer's JEDEC ID Code 65-71 Manufacturer's JEDEC Code (Cont.) 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continuted) 93 Year of Manufacture in BCD 94 Week of Manufacture in BCD 95-98 Module Serial Number 99-127 Manufacturer-Specific Data (Rsvd) 09005aef80948ad4 SD2_4C4_8_16_32x32UDG ...

Page 26

... Figure 11: 100-Pin DIMM Dimensions – 16MB 0.079 (2.00) R (2X) U1 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) PIN 1 TYP No Components This Side of Module PIN 100 NOTE: All dimensions in inches (millimeters); 09005aef80948ad4 SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN 16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR) Front View 3.557 (90.34) 3.545 (90.04 ...

Page 27

Figure 12: 100-Pin DIMM Dimensions – 32MB, 64MB, and 128MB 0.079 (2.00) R (2X) U1 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) PIN 1 TYP PIN 100 NOTE: All dimensions in inches (millimeters); Data Sheet Designation Released (No Mark): ...

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