MT4LSDT3232UDG-8D1 Micron Technology Inc, MT4LSDT3232UDG-8D1 Datasheet - Page 11

• Manufacturer Part Number: MT4LSDT3232UDG-8D1
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT3232UDG-8D1

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 6ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 274mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / Rohs Status: Not Compliant

Commands
Table provides a general reference of available com-
mands. For a more detailed description of commands
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
09005aef80948ad4
SD2_4C4_8_16_32x32UDG.fm - Rev. A 12/04 EN
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. A0–A11(32MB) or A0–A12 (64MB, 128MB, and 128MB) provide row address and BA0 and BA1 determine which bank is
2. A0–A8 (16MB and 32MB) or A0–A8 (64MB and 128MB) provide column address; A10 HIGH enables the auto precharge
3. A10 LOW: BA0 and BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0 and
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 (32MB) or A0–A12 (64MB, 128MB, and 128MB) define the op-code written to the Mode Register.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9, Commands and DQMB Operation Truth
made active.
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is
being read from or written to.
BA1 are “Don’t Care.”
Commands and DQMB Operation Truth Table
NAME (FUNCTION)
16MB (x32, SR); 32MB, 64MB, 128MB (x32, DR)
S#
H
L
L
L
L
L
L
L
L
–
–
11
RAS# CAS# WE# DQMB
and operations, refer to the 64Mb, 128Mb, or 256Mb
SDRAM component data sheet.
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
100-PIN SDRAM UDIMM
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
7
7
Bank/Row
Bank/Col
Bank/Col
Op-Code
©2004 Micron Technology, Inc. All rights reserved.
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQS
X
X
X
X
X
X
X
NOTES
4, 5
1
2
4
3
6
7
7