PEF80912HV14XT Lantiq, PEF80912HV14XT Datasheet - Page 25

• Manufacturer Part Number: PEF80912HV14XT
• Manufacturer: Lantiq

Specifications of PEF80912HV14XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

– DEA Deactivation bit
– CSO Cold Start Only
– UOA U-Only Activation
– SAI
– FEBE Far-end Block Error
– PS1
– PS2
– NTM NT-Test Mode
– AIB
– NIB
– SCO Start on Command only bit
– 1
The principle signal flow is depicted in
in bits that are covered by the CRC and bits that are not. After the CRC generation the
bits are arranged in the proper sequence according to the 2B1Q frame format, encoded
and finally transmitted.
In receive direction the data is first decoded, descrambled, deframed and handed over
for further processing.
•
Figure 7
Data Sheet
can be accessed by the system interface for proprietary use
M
U
X
S-Activity Indicator
Power Status Primary Source
Power Status Secondary Source PS2 = (1) –> Secondary power supply ok
Alarm Indication Bit
Network Indication Bit
(currently not defined by ANSI/ETSI)
U
2B1Q Encoding
Sy nc/Inv. Sy nc
2B1Q
Tone/Pulse
Patterns
Framer - Data Flow Scheme
Control
Scrambler
FEBE = (0) –> Far-end block error occurred
CSO = (1) –> NT-activation with cold start only
UOA = (0) –> U-only activated
NTM = (0) –> NT busy in test mode
DEA = (0) –> LT informs NT that it will turn off
Figure 7
PS1 = (1) –> Primary power supply ok
SAI = (0) –> S-interface is deactivated
AIB = (0) –> Interruption (according to ANSI)
NIB = (1) –> no function (reserved for network use)
17
M
U
X
and
M
Figure
U
X
M1,2,3 (EOC)
2B+D, M4
M5,6 except CRC
CRC Generation
(M-bit handling acc. to ETR080)
8. The data is first grouped
Functional Description
U
2B1Q
PEF 80912/80913
-Fram e r
M
U
X
uframer.emf
2001-03-29
2B+D
M4