PEF80912HV14XT Lantiq, PEF80912HV14XT Datasheet - Page 37

• Manufacturer Part Number: PEF80912HV14XT
• Manufacturer: Lantiq

Specifications of PEF80912HV14XT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEF 80912/80913
Functional Description
Pending Timing
In the NT-mode the pending timing state assures that the C/I-channel code DC is issued
four times before entering the ’Deactivated’ state.
Receive Reset
In state ’Receive Reset’ a reset of the Uk0-receiver is performed, except in case that
state ’Receive Reset’ was entered from state ’Pend. Deact. U’. Timer T7 assures that no
activation procedure is started from the NT-side for a minimum period of time of T7. This
gives the LT a chance to activate the NT.
Reset
In state ’Reset’ a software-reset is performed.
Synchronized 1
State ’Synchronized 1’ is the fully active state of the U-transceiver, while the downstream
device is deactivated.
Synchronized 2
In this state the U-transceiver has received UOA = 1. This is a request to activate the
downstream device.
Test
The test signal SSP is issued as long as TM2-0 = ’101’ . For further details see
Table
9.
Transparent
This state is entered upon the detection of ACT = 1 received from the LT-side and
corresponds to the fully active state.
Wait for ACT
Upon the receipt of AI, the NT waits for a response (ACT = 1) from the LT-side.
Wait for SF
The signal SN2 is sent on the U-interface and the receiver waits for detection of the
superframe.
Wait for SF AL
This state is entered in the case of an analog loop-back and allows the receiver to update
the AGC, to recover the timing phase, and to update the EQ-coefficients.
Data Sheet
29
2001-03-29