RCGD16589FB Intel, RCGD16589FB Datasheet

RCGD16589FB

Manufacturer Part Number

RCGD16589FB

Description

Manufacturer

Intel

Datasheet

1.RCGD16589FB.pdf (17 pages)

Specifications of RCGD16589FB

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

132

Lead Free Status / Rohs Status

Not Compliant

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General Description

GD16585 and GD16589 are transmitter

chips used in SDH STM-64 and SONET

OC-192 optical communication systems.

The device is available in two versions:

Except the different operating bit rate the

two versions are functional identical.

The transmitter integrates the main func-

tions of the serializer which are:

The CMU consists of Phase Locked

Loop (PLL) controlled from an external

reference clock. The PLL characteristics

are controlled by an external loop filter al-

lowing the user to optimize the jitter

perfomance of the device.

The 16:1 Multiplexer accepts 16 parallel

input bits at 622.88 Mbit/s (or 666 Mbit/s)

that are serialized into a 9.9538 Gbit/s (or

10.66 Gbit/s) data stream. The serialized

CKOUTN

CKOUT

DIN15

SEL1

SEL2

CKIN

DIN0

DI15

CKI

DI0

GD16585 for 9.5328 Gbit/s.

GD16589 for 10.66 Gbit/s with

Forward Error Correction (FEC).

Clock Multiply Unit (CMU)

16:1 Multiplexer in a single monolithic

IC.

Input Data

Parallel

Selector

Phase

PFCX

Multiplexer

16:1

PCTLX

SGNX

Control

Timing

data stream is re-timed by the high-

speed clock from the VCO.

The parallel input interface features

GIGA’s unique self-synchronizing dy-

namic phase alignment scheme that al-

lows both:

These schemes enable the serializer to

absorb output delay variations from the

upstream System ASIC without use of

initialization or reset.

The data and clock inputs to the MUX

are LVDS and the output data is CML

compatible.

The device operates from a dual -5.2 V

and +3.3 V power supply. The power dis-

sipation is 2.2 W, typical.

The device is manufactured in a Silicon

Bipolar process and packaged in an 132

balls 13 × 13 mm Ceramic/Plastic Ball

Grid Array (CBGA).

Source synchronous counter clocking

for OIF99.102.5 interfaces.

Forward clocking with phase nulling

and jitter clean-up of the clock.

SEL3

REFCK/N

Frequency

VCC

Detector

VCO

Phase

VDD

VDDO VDDA VEE

VCUR

OUT

OUTN

VCTL

PCTL

(PHIGH)

(PLOW)

NLDET

TCK

10 Gbit/s

Transmitter MUX

with Re-timing

GD16585/GD16589

(FEC)

Preliminary

Features

Applications

PLL based CMU with on-chip 10 GHz

or 10.66 GHz VCO.

16:1 Multiplexer with a last stage

re-timing.

OIF99.102.5 compliant timing .

LVDS compatible parallel data and

clock inputs

CML compatible serial data output.

155 MHz or 622 MHz reference clock

input (selectable).

Divide by 16 clock output.

PLL out of lock detector.

Dual supply operation: -5.2 V and

+3.3 V

Low power dissipation: 2.2 W (typ.).

Available in three package versions:

– EB: 132 ball (16 mill) Ceramic

– EF: 132 ball (20 mill) Ceramic

– FB: 132 ball (20 mill) Plastic

Available in two versions:

– GD16585 for 10 Gbit/s

– GD16589 for 10.66 Gbit/s

Telecommunication systems:

– SDH STM-64

– SONET OC-192

– Optical Transport Networking

– FEC applications

Fibre optic test equipment.

BGA 13 × 13 mm

(OTN)

Data Sheet Rev.: 13

Related parts for RCGD16589FB

RCGD16589FB Summary of contents

Page 1

... Intel company General Description GD16585 and GD16589 are transmitter chips used in SDH STM-64 and SONET OC-192 optical communication systems. The device is available in two versions: GD16585 for 9.5328 Gbit/s. u GD16589 for 10.66 Gbit/s with u Forward Error Correction (FEC). Except the different operating bit rate the two versions are functional identical ...

Page 2

Functional Details The main function of GD16585/GD16589 is as transmitter in STM-64 /OC-192 and OTN optical communication systems. It integrates: Voltage Controlled Oscillator (VCO) u Phase and Frequency Detector (PFD) u 16:1 Multiplexer u Re-timing of output data. u Phase ...

Page 3

If no adjustement is needed the VCUR can be lefted open. With AC coupled outputs the VCUR pin must not be directly connected which may cause the output stage to saturate deteriorating the eye-diagram. Refer to Figure ...

Page 4

Application Framer + Out of Lock - Figure 1. Application Information, OIF interface to the Framer. Pin D1 Pin D2 VDD VEE Pin VDDO VEE C is 10nF parallel with ...

Page 5

Gbit/s Output Interface GD16585/GD16589 0V 50W -5.2V Figure 3. 10 Gbit/s outputs (OUT/OUTN), DC coupled. GD16585/GD16589 0V 50W -5.2V Figure 4. 10 Gbit/s outputs (OUT/OUTN), AC coupled. Note: With AC coupled outputs VCUR must not be connected directly to ...

Page 6

Mbit/s Output Interface GD16585 50 MSL W 8mA -5.2V Figure 5. Open collector output. Open collector outputs should always be terminated at the receiver end, by preferably 50 W. 622 Mbit/s Input Interface LVDS Output Figure 6. LVDS compatible ...

Page 7

Pin List Mnemonic: Pin No.: DI0, DIN0 C7, D7 DI1, DIN1 A8, B8 DI2, DIN2 A9, B9 DI3, DIN3 B10, A11 DI4, DIN4 C11, C12 DI5, DIN5 D12, E12 DI6, DIN6 G11, H12 DI7, DIN7 J12, J11 DI8, DIN8 L9, ...

Page 8

Mnemonic: Pin No.: VEE B2, C8, C10, D8, D10, J4, J9, K4, K9 VCC D11, J7, J10 (K10 A10, A12, B11-12, C9, D9, F12, G12, K7, K11, L7, L10, M1, M6, M7, M10-12 NC D3-4, J3 Package Pinout ...

Page 9

(empty) = VDD Figure 9. Package FB Pinout. Top view seen through the package. Data Sheet Rev ...

Page 10

Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in table are referred to VDD/VDDA. All currents are defined positive out of the pin. VDD GND Symbol: Characteristic: V Negative ...

Page 11

DC Characteristics ° °C. VEE = -5.2 V. VCC = +3.3 V. VDD GND. CASE All voltages in table are referred to VDD. All currents are defined positive out of ...

Page 12

AC Characteristics, General ° °C, VEE = -5.2 V. VCC = +3.3 V. CASE Symbol: Characteristic: J Jitter transfer TRF J Jitter generation GEN V 10 Gbit/s output voltage OUT OUT/OUTN output reflection coefficient G ...

Page 13

AC Characterisitcs, Source Synchronous Clocking - OIF99.102 ° °C, VEE = -5.2 V. CASE Framer OIF99.102.5 TXDATA TXCLK TXCLK_SRC 2 -5.2 V 155/622 MHz Figure 10. OIF interface. CKI DI0-15 Figure 11. Timing relation ...

Page 14

AC Characteristics, Forward Clocking to System ASIC ° °C, VEE = -5.2 V. CASE System ASIC TXDATA TXCLK -5.2 V Figure 12. Forward clocking with phase nulling circuit. CKI CKOUT DI0-15 0 Figure ...

Page 15

Package Outline EF - Package Figure 14. Package 132 ball Ceramic BGA (EB and EF package). Data Sheet Rev.: 13 GD16585/GD16589 Page ...

Page 16

Figure 15. Package 132 ball Plastic BGA (FB package). Data Sheet Rev.: 13 GD16585/GD16589 Page ...

Page 17

... Please check our Internet web site for latest version of this data sheet. GD16589-<XX> <Wafer #>-<Lot #> <Intel FPO #> <Die ID> Package Type: Intel Order Number: HCGD16585EB 132 ball (16 mil) Ceramic BGA MM# 835479 HCGD16585EF 132 ball (20 mil) Ceramic BGA MM# 837348 RCGD16585FC ...

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