MT8HTF12864AZ-800H1 Micron Technology Inc, MT8HTF12864AZ-800H1 Datasheet - Page 10

• Manufacturer Part Number: MT8HTF12864AZ-800H1
• Description: MODULE DDR2 SDRAM 1GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT8HTF12864AZ-800H1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240DIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.28A
• Number Of Elements: 8
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 800MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Compliant

I
Table 8: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef83b94f21
htf8c128x64az – Rev. B 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
puts are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current (standard): CK and CK# at 0V; CKE ≤ 0.2V; Other con-
trol and address bus inputs are floating; Data bus inputs are floating
DD
RCD (I
CK (I
RP (I
OUT
RP =
DD
),
= 0mA; BL = 4, CL = CL (I
DD
DD
Specifications
t
t
RAS =
DD
RP (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
),
DD
t
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
t
RP (I
DD
t
CK =
Specifications and Conditions – 1GB
DD
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
CK (I
), AL = 0;
),
t
RC =
DD
t
CK =
); REFRESH command at every
t
RC (I
t
CK =
t
CK (I
DD4W
DD
t
),
DD
CK (I
t
),
RAS =
t
CK =
t
t
RAS =
CK =
DD
t
CK =
),
t
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
CK (I
t
OUT
t
CK =
t
RAS MAX (I
1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
t
CK (I
CK =
10
DD
= 0mA; BL = 4, CL
DD
t
),
t
DD
RAS MAX (I
CK (I
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
t
CK (I
); CKE is
RAS =
t
DD
RC =
t
RFC (I
DD
),
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
t
),
); CKE
RC
RAS
DD
t
RP =
DD
)
),
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
-1GA
1040
1680
1680
2120
920
480
480
400
560
56
80
56
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
-80E/-
1280
1280
1880
800
720
880
400
400
320
480
56
80
56
Specifications
1080
1080
1720
-667
680
800
320
320
240
440
56
80
56
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA