LM97593VH/HALF National Semiconductor, LM97593VH/HALF Datasheet - Page 24

• Manufacturer Part Number: LM97593VH/HALF
• Manufacturer: National Semiconductor

Specifications of LM97593VH/HALF

• Lead Free Status / Rohs Status: Compliant

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Functional Description
The LM97593 contains two identical 12-bit ADCs driving the
digital down-conversion (DDC) circuitry shown in the block
diagram in Figure 16.
ADC
The ADCs operate off of a +3.3V supply and use a pipeline
architecture with error correction circuitry to help ensure max-
imum performance. The differential analog input signal is
digitized to 12 bits. The user has the choice of using an inter-
nal 1.0 Volt or an external reference. Any external reference
is buffered on-chip to ease the task of driving that pin.
The clock frequency is rated up to 65 MHz. The analog input
for both channels is acquired at the rising edge of the clock.
The digital data for a given sample is delayed by the pipeline
for 7 clock cycles before it reaches the input to the DDC cir-
cuit. A logic high on the power down (PD) pin reduces the
converter power consumption to 50 mW. The DDC power can
be further reduced by gating off the clock as described in sec-
tion 7.0 Power Management.
DDC
Each independent DDC channel down converts the sub-sam-
pled IF to baseband, decimates the signal rate by a pro-
grammable factor ranging from 32 to 16384, provides channel
filtering, and outputs quadrature symbols.
A crossbar switch enables either of the two inputs or a test
register to be routed to either DDC channel. Flexible channel
filtering is provided by the two programmable decimating FIR
FIGURE 16. LM97593 Dual ADC / Digital Tuner / AGC Block Diagram with Control Register Associations
24
filters. The final filter outputs can be converted to a 12-bit
floating point format or standard two’s complement format.
The output data is available at both serial and parallel ports.
The LM97593’s DDC maintains over 100 dB of spurious free
dynamic range and over 100 dB of out-of-band rejection. This
allows considerable latitude in channel filter partitioning be-
tween the analog and digital domains.
The frequencies, phase offsets, and phase dither of the two
sine/cosine numerically controlled oscillators (NCOs) can be
independently specified. Two sets of coefficient memories
and a crossbar switch allow shared or independent filter co-
efficients and bandwidth for each channel. Both channels
share the same decimation ratio and input/output formats.
Each channel has its own AGC circuit for use with narrowband
radio channels where most of the channel filtering precedes
the ADC. The AGC closes the loop around the DVGA, com-
pressing the dynamic range of the signal into the ADC. AGC
gain compensation in the LM97593 removes the DVGA gain
steps at the output. The time alignment of this gain compen-
sation circuit can be adjusted. The AGC can be configured to
operate continuously or set to a fixed gain. The two AGC cir-
cuits operate independently but share the same programmed
parameters and control signals.
The chip receives configuration and control information over
a microprocessor-compatible bus consisting of an 8-bit data
I/O port, an 8-bit address port, a chip enable strobe, a read
strobe, and a write strobe. The chip’s control registers (8 bits
each) are memory mapped into the 8-bit address space of the
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