LM97593VH/HALF National Semiconductor, LM97593VH/HALF Datasheet - Page 9

• Manufacturer Part Number: LM97593VH/HALF
• Manufacturer: National Semiconductor

Specifications of LM97593VH/HALF

• Lead Free Status / Rohs Status: Compliant

Clock Input
F
t
t
Control Interface
t
t
t
t
t
t
t
DVGA Interface
t
t
Parallel Output Interface
t
t
t
t
t
Serial Interface
t
t
t
t
t
t
JTAG Interface
t
t
t
t
t
t
t
t
t
t
t
CKDC
RF
MRA
MRIC
MRSU
MRH
SISU
SIH
SIW
STIW
GSTB
OENV
OENT
SELV
POV
DBG
SFSV
OV
RDYW
DCMSU
DCMH
RDYV
JPCO
JSCO
JPDZ
JSDZ
JPEN
JSEN
JSSU
JPSU
JSH
JPH
JCH
CK
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = D18GND = 0V, V
(±10%), V
48, F2 Decimation = 2. Typical values are for T
T
Symbol
A
= 25°C. (Note 13)
D18
= +1.8V (±10%), Internal V
Clock (CK) Frequency (Figure 6)
CK duty cycle, DCS off (Figure 6)
CK rise and fall times (V
NCO Tuning Resolution
NCO Phase Resolution
MR Active Time (Figure 4)
MR Inactive to first Control Port Access (Figure 4)
MR Setup Time to CK (Figure 4)
MR Hold Time from CK (Figure 4)
SI Setup Time to CK (Figure 5)
SI Hold Time from CK (Figure 5)
SI Pulse Width (Figure 5)
A|BSTROBE Inactive Pulse Width (Figure 7)
A|BGAIN setup before A|BSTROBE (Figure 7)
POUT_EN Active to POUT[15:0] Valid (Figure 9)
POUT_EN Inactive to POUT[15:0] Tri-State (Figure 9)
PSEL[2:0] to POUT[15:0] Valid (Figure 10)
RDY to POUT[15:0] New Value Valid (Note 5) (Figure 11)
SCK to POUT[15:0], RDY, SFS, AOUT, BOUT Valid (Figure 12)
SCK to SFS Valid (Note 3) (Figure 13)
SCK to A|BOUT Valid (Note 4) (Figure 13)
RDY Pulse Width (Figure 13)
PSEL[2:0] Setup Time to SCK_IN (Figure 8)
PSEL[2:0] Hold Time from SCK_IN (Figure 8)
SCK to RDY valid (Figure 13)
Propagation Delay TCK to TDO (Figure 14)
Propagation Delay TCK to Data Out (Figure 14)
Disable Time TCK to TDO (Figure 14)
Disable Time TCK to Data Out (Figure 14)
Enable Time TCK to TDO (Figure 14)
Enable Time TCK to Data Out (Figure 14)
Setup Time Data to TCK (Figure 14)
Setup Time TDI, TMS to TCK (Figure 14)
Hold Time Data to TCK (Figure 14)
Hold Time TCK to TDI, TMS (Figure 14)
TCK Pulse Width High (Figure 14)
Parameter (C
IL
to V
REF
= +1.0V, f
IH
) (Figure 6)
A
= 25°C. Boldface limits apply for T
L
=50pF)
CLK
= 65 MHz, V
9
CM
= V
COM
, t
R
= t
MIN
F
Min
= 1 ns, C
0.5
≤
20
40
10
10
10
45
45
50
-2
-2
-3
4
6
2
6
2
4
6
3
0
0
T
A
≤
T
Typical
L
MAX
0.005
(Note
= 5 pF/pin. CIC Decimation =
0.02
-0.9
10)
1.6
1.7
1.4
1.8
2
2
. All other limits apply for
A
= V
Max
3.5
3.5
65
60
12
10
13
25
35
25
35
25
35
2
7
4
4
D
= V
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DR
CK periods
CK periods
CK periods
CK periods
CK periods
= +3.3V
Units
MHz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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