HI5660/6IA Intersil, HI5660/6IA Datasheet - Page 8

• Manufacturer Part Number: HI5660/6IA
• Description: IC DAC 8-BIT 60MSPS 28-TSSOP
• Manufacturer: Intersil

Specifications of HI5660/6IA

• Settling Time: 15ns
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 165mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

inputs are 50Ω lines, then 50Ω termination resistors should
be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then
all of the digital functions of the device and their
corresponding components should be over the digital ground
plane and terminated to the digital ground plane. The same
is true for the analog components and the analog ground
plane.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should
be placed as close as possible to the converter’s power
supply pins, AV
designed using separate digital and analog ground planes,
these capacitors should be terminated to the digital ground
for DV
filtering of the power supplies on the board is
recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ± 60 ppm /
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO
pin (16) selects the reference. The internal reference can
be selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (to the
analog supply voltage) and the external reference driven
into REFIO, pin 17. The full scale output current of the
converter is a function of the voltage reference used and
the value of R
range, through operation below 2mA is possible, with
performance degradation.
If the internal reference is used, V
approximately 1.16V (pin 18). If an external reference is
used, V
calculation for I
I
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
resistor, then the input coding to output current will resemble
the following:
OUT
INPUT CODE (D7-D0)
(Full Scale) = (V
DD
1000 0000
0000 0000
TABLE 1. INPUT CODING vs OUTPUT CURRENT
1111 1111
FSADJ
and to the analog ground for AV
SET
will equal the external reference. The
OUT
DD
. I
and DV
OUT
(full scale) is:
FSADJ
should be within the 2mA to 20mA
IOUTA (mA)
DD
/R
8
. Also, should the layout be
SET
20
10
0
o
C drift coefficient over the
FSADJ
) x 32.
will equal
DD
IOUTB (mA)
. Additional
SET
10
20
0
HI5660
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. R
chosen so that the desired output voltage is produced in
conjunction with the output full scale current, which is
described above in the ‘Reference’ section. If a known line
impedance is to be driven, then the output load resistor
should be chosen to match this impedance. The output
voltage equation is:
V
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mV
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
OUT
OUT
HI5660
PIN 21
PIN 22
= I
= 2 x I
OUT
OUT
X R
IOUTA
IOUTB
x R
LOAD
EQ
.
, where R
100Ω
50Ω
50Ω
FIGURE 4.
EQ
is ~12.5Ω.
LOAD
V
OUT
50Ω
P-P
= (2 x I
should be
amplitude
OUT
x R
EQ
)V