LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 49

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.0
7.1
7.1.1
Datasheet
Figure 13. PCI Configuration Registers
Configuration Registers
The 82551ER acts as both a master and a slave on the PCI bus. As a master, the 82551ER interacts
with the system main memory to access data for transmission or deposit received data. As a slave,
some 82551ER control structures are accessed by the host CPU to read or write information to the
on-chip registers. The CPU also provides the 82551ER with the necessary commands and pointers
that allow it to process receive and transmit data.
Function 0: LAN (Ethernet) PCI Configuration Space
The 82551ER PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in
PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82551ER are both read only word entities. Their values are:
Vendor ID: 8086h
Device ID: 1209h
Reserved
Max_Lat
Power Management Capabilities
BIST
Figure
Subsystem ID
13.
Device ID
Status
Flash Memory Mapped Base Address Register
CSR Memory Mapped Base Address Register
Header Type
CSR I/O Mapped Base Address Register
Expansion ROM Base Address Register
Class Code
Min_Gnt
Reserved
Reserved Base Address Register
Reserved Base Address Register
Reserved Base Address Register
Data
Reserved (PCI mode)
Reserved
Latency Timer
Next Item Ptr
Interrupt Pin
Power Management CSR
Subsystem Vendor ID
Command
Vendor ID
Networking Silicon — 82551ER
Cache Line Size
Interrupt Line
Capability ID
Revision ID
Cap_Ptr
DCh
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
E0h
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