LU82551ER 860613 Intel, LU82551ER 860613 Datasheet - Page 5

• Manufacturer Part Number: LU82551ER 860613
• Manufacturer: Intel

Specifications of LU82551ER 860613

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.0
10.0
11.0
12.0
Datasheet
8.2
PHY Unit Registers ..........................................................................................................61
9.1
9.2
9.3
82551ER Test Port Functionality...................................................................................... 71
10.1
10.2
Electrical and Timing Specifications................................................................................. 75
11.1
11.2
11.3
11.4
Package and Pinout Information ...................................................................................... 89
12.1
12.2
8.1.8
8.1.9
Statistical Counters ............................................................................................. 57
MDI Registers 0 - 7 ............................................................................................. 61
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
MDI Registers 8:15..............................................................................................64
MDI Register 16:31 ............................................................................................. 65
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter ..................... 68
9.3.11 Register 26: Equalizer Control and Status Register .............................. 68
9.3.12 Register 27: PHY Unit Special Control Register ................................... 68
9.3.13 Register 28: MDI/MDI-X Control Register .............................................. 69
9.3.14 Register 29: Hardware Integrity Control Register .................................. 69
Introduction.......................................................................................................... 71
Test Function Description.................................................................................... 71
10.2.1 Tristate ................................................................................................... 71
10.2.2 XOR Tree ............................................................................................... 72
Absolute Maximum Ratings................................................................................. 75
DC Specifications ............................................................................................... 76
AC Specifications ................................................................................................ 80
Timing Specifications .......................................................................................... 81
11.4.1 Clocks Specifications ............................................................................. 81
11.4.2 Timing Parameters ................................................................................. 82
Package Information ........................................................................................... 89
Pinout Information ............................................................................................... 91
12.2.1 Pin Assignments .................................................................................... 91
12.2.2 Ball Grid Array Diagram ......................................................................... 93
Receive Direct Memory Access Byte Count........................................... 56
Flow Control Register............................................................................. 56
Register 0: Control Register .................................................................. 61
Register 1: Status Register ................................................................... 62
Register 2: PHY Identifier Register ....................................................... 63
Register 3: PHY Identifier Register ....................................................... 63
Register 4: Auto-Negotiation Advertisement Register ........................... 63
Register 5: Auto-Negotiation Link Partner Ability Register .................... 64
Register 6: Auto-Negotiation Expansion Register ................................. 64
Register 16: PHY Unit Status and Control Register .............................. 65
Register 17: PHY Unit Special Control Register ................................... 65
Register 18: PHY Address Register ....................................................... 66
Register 19: 100BASE-TX Receive False Carrier Counter ................... 66
Register 20: 100BASE-TX Receive Disconnect Counter ...................... 67
Register 21: 100BASE-TX Receive Error Frame Counter .................... 67
Register 22: Receive Symbol Error Counter ......................................... 67
Register 23: 100BASE-TX Receive Premature End of Frame Error Coun-
ter 67
Register 24: 10BASE-T Receive End of Frame Error Counter ............. 67
Networking Silicon — 82551ER
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