TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet - Page 27

• Manufacturer Part Number: TXC-06312BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06312BIOG

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2 7 o f 2 0 2
REFONESECCLK
REFTXFS
REFSYSFS
RESET
DCCRXDATA1
DCCRXDATA2
DCCRXDATA3
Symbol
Symbol
RECEIVE DCC INTERFACES
Lead No. I/O/P
Lead No.
U4
V2
Y1
B21
R1
R2
A4
O
O
O
I/O/P
O
I
I
I
LVCMOS
LVCMOS
LVCMOS
Type
4mA
4mA
4mA
LVCMOS
LVTTLp Hardware Reset (Active Low): The use of this lead at
LVTTL One Second Clock: Optional one second reference for
LVTTL Transmit Reference Frame Sync: Optional 8 kHz refer-
Type
- Lead Descriptions -
8mA
Receive DCC Data #1: Bit-serial data from the TOH monitor of
receive line interface #1 to an external LAPD interface control-
ler or similar device.
This data can be optionally selected to provide D1-D3 (RS/
Section DCC) or D4-D12 (MS/Line DCC).
Receive DCC Data #2: Bit-serial data from the TOH monitor of
receive line interface #2 to an external LAPD interface control-
ler or similar device.
This data can be optionally selected to provide D1-D3 (RS/
Section DCC) or D4-D12 (MS/Line DCC).
Receive DCC Data #3: Bit-serial data from the TOH monitor of
receive line interface #3 to an external LAPD interface control-
ler or similar device.
This data can be optionally selected to provide D1-D3 (RS/
Section DCC) or D4-D12 (MS/Line DCC).
performance monitoring counters.
This is a 1.0 Hz ± 32 ppm clock input which is asynchro-
nous with other clock inputs/outputs, and has a minimum
pulse width of 2 77.76 MHz clock cycles = 25.72 ns
(because synchronized). If used, the one second counters
are shadowed after detection of the rising edge of this
input.
ence frame sync pulse. If present, this input must be syn-
chronous to LINETXCLK and shall be at least 1 77.76 MHz
clock cycle wide = 12.86 ns.
System Reference Frame Sync: 8 kHz reference frame
sync pulse. This output has a pulse width of 1 77.76 MHz
clock cycle (= 12.86 ns) and shall be synchronous to the
LINETXCLK when this last one is not divided down to
19.44 MHz.
power-up is mandatory. Holding this lead for at least 50 ns
causes all the registers in the device to be reset.
Name/Function
Name/Function
PRELIMINARY TXC-06312B-MB, Ed. 2
PHAST-12N Device
DATA SHEET
TXC-06312B
June 2005