SC16C554BIBS,157 NXP Semiconductors, SC16C554BIBS,157 Datasheet - Page 12

• Manufacturer Part Number: SC16C554BIBS,157
• Manufacturer: NXP Semiconductors

Specifications of SC16C554BIBS,157

• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 2.
SC16C554B_554DB
Product data sheet
Symbol
INTSEL
IOR
IOW
IRQ
n.c.
Pin description
Pin
PLCC68 LQFP64 LQFP80 HVQFN48
65
52
18
15
21, 49,
52, 54,
55, 65
-
40
9
-
-
…continued
6
70
31
-
1, 10,
20, 21,
30, 40,
41, 49,
52, 60,
61, 71,
80
All information provided in this document is subject to legal disclaimers.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
-
33
7
4
-
Rev. 4 — 8 June 2010
Type
I
I
I
O
-
Description
Interrupt Select (active HIGH, with internal
pull-down). This function is associated with the
16 mode only. When the 16 mode is selected, this pin
can be used in conjunction with MCR[3] to enable or
disable the 3-state interrupts, INTA to INTD, or override
MCR[3] and force continuous interrupts. Interrupt
outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR[3] to
control the 3-state interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-state outputs.
This pin is disabled in the 68 mode. Due to pin
limitations on the 64-pin packages, this pin is not
available. To cover this limitation, the
SC16C554DBIB64 version operates in the continuous
interrupt enable mode by bonding this pin to V
internally. The SC16C554BIB64 operates with MCR[3]
control by bonding this pin to GND. The INTSEL pin is
not available on the HVQFN48 package.
Input/Output Read strobe (active LOW). This
function is associated with the 16 mode only. A logic 0
transition on this pin will load the contents of an internal
register defined by address bits A0 to A2 onto the
SC16C554B/554DB data bus (D0 to D7) for access by
external CPU. This pin is disabled in the 68 mode.
Input/Output Write strobe (active LOW). This
function is associated with the 16 mode only. A logic 0
transition on this pin will transfer the contents of the
data bus (D0 to D7) from the external CPU to an
internal register that is defined by address bits
A0 to A2. When the 68 mode is selected, this pin
functions as R/W (see definition under R/W).
Interrupt Request or Interrupt ‘A’. This function is
associated with the 68 mode only. In the 68 mode,
interrupts from UART channels A to D are wire-ORed
internally to function as a single IRQ interrupt. This pin
transitions to a logic 0 (if enabled by the Interrupt
Enable Register) whenever a UART channel(s)
requires service. Individual channel interrupt status can
be determined by addressing each channel through its
associated internal register, using CS and A3 to A4. In
the 68 mode, and external pull-up resistor must be
connected between this pin and V
this pin changes to INTA when operating in the
16 mode (see definition under INTA).
not connected
SC16C554B/554DB
CC
© NXP B.V. 2010. All rights reserved.
. The function of
CC
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