MT41J256M8HX-125:D Micron Technology Inc, MT41J256M8HX-125:D Datasheet - Page 153

• Manufacturer Part Number: MT41J256M8HX-125:D
• Description: MICMT41J256M8HX-125:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-125:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 185mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Compliant

ACTIVATE Operation
Figure 65: Example: Meeting
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command
Address
BA[2:0]
CK#
CK
Bank x
ACT
Row
T0
NOP
T1
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE com-
mand, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the
is programmed correctly, a READ or WRITE command may be issued prior to
(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to
ment that (ACTIVATE-to-READ/WRITE) + AL ≥
TIVE Latency).
the next whole number to determine the earliest clock edge after the ACTIVATE com-
mand on which a READ or WRITE command can be entered. The same procedure is
used to convert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is
defined by
given
parameter applies, regardless of the number of banks already opened or closed.
t RRD
t
FAW (MIN) period, and the
NOP
t
T2
RRD (MIN) and
t
RRD. No more than four bank ACTIVATE commands may be issued in a
t
RCD (MIN) should be divided by the clock period and rounded up to
Bank y
Row
ACT
T3
t
RCD (MIN)
NOP
T4
153
t
RRD (MIN) restriction still applies. The
t
RCD specification. However, if the additive latency
NOP
T5
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CCD (MIN).
t RCD
2Gb: x4, x8, x16 DDR3 SDRAM
t
NOP
RCD (MIN) (see POSTED CAS ADDI-
T8
t
RCD (MIN) with the require-
NOP
Indicates A Break in
Time Scale
T9
ACTIVATE Operation
© 2006 Micron Technology, Inc. All rights reserved.
NOP
T10
t
FAW (MIN)
t
RCD
RD/WR
Bank y
Don’t Care
T11
Col
t
RC.