MT41J256M8HX-125:D Micron Technology Inc, MT41J256M8HX-125:D Datasheet - Page 195

• Manufacturer Part Number: MT41J256M8HX-125:D
• Description: MICMT41J256M8HX-125:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-125:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 185mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 800MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / Rohs Status: Compliant

Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
ODT
ODT
CK#
CK#
R
DQ
DQ
R
CK
CK
TT
TT
NOP
NOP
T0
T0
WRS4
WRS4
Valid
Valid
T1
T1
Notes:
Notes:
NOP
NOP
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. In this example ODTH4 = 4 is satisfied exactly.
T2
T2
ODTL
ODTL
ODTL on
ODTL on
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
ODT can remain HIGH. R
cnw
cnw
ODTH4
NOP
ODTH4
NOP
T3
T3
WL
WL
NOP
NOP
T4
T4
ODTL
ODTL
t AON (MIN)
t AON (MIN)
cwn
cwn
t ADC (MAX)
t ADC (MAX)
NOP
4
NOP
4
T5
TT(WR)
T5
195
is enabled.
R
R
NOP
TT(WR)
NOP
tt
T6
R
DI
T6
n
DI
n
TT(WR)
_
TT,nom
TT,nom
wr
ODTL off
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n + 1
n + 1
DI
DI
and R
can be either enabled or disabled. If disabled,
NOP
n + 2
NOP
T7
n + 2
DI
T7
DI
2Gb: x4, x8, x16 DDR3 SDRAM
TT(WR)
n + 3
n + 3
DI
DI
NOP
NOP
T8
T8
are enabled.
ODTL off
t ADC (MIN)
t ADC (MAX)
t AOF (MIN)
t AOF (MAX)
NOP
© 2006 Micron Technology, Inc. All rights reserved.
NOP
T9
T9
Transitioning
Transitioning
R
TT,nom
NOP
T10
NOP
T10
t AOF (MIN)
t AOF (MAX)
NOP
Don’t Care
T11
Don’t Care
NOP
T11