MT48H32M16LFCJ-75 Micron Technology Inc, MT48H32M16LFCJ-75 Datasheet - Page 17

• Manufacturer Part Number: MT48H32M16LFCJ-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFCJ-75

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 8:
Temperature-Compensated Self Refresh (TCSR)
Partial-Array Self Refresh (PASR)
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
EMR Definition
Notes:
1. All banks (banks 0, 1, 2, and 3).
2. Two banks (banks 0 and 1; BA1=0).
3. One bank (bank 0; BA1 = BA0 = 0).
4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0).
5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB - 1 = 0).
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The extended mode register must be programmed with E7 through E12 set to “0.” It
must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either
of these requirements results in unspecified operation. Once the values are entered, the
extended mode register settings will be retained even after exiting deep power-down
mode.
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator. Programming of the TCSR bits will have
no effect on the device. The self refresh oscillator will continue refresh at the factory
programmed optimal rate for the device temperature.
For further power savings during self refresh, the partial-array self refresh (PASR) feature
allows the controller to select the amount of memory that will be refreshed during self
refresh. The following refresh options are available.
E14
E12
0
–
0
0
1
1
E11
E13
0
–
0
1
0
1
E10
Mode Register Definintion
Standard mode register
Reserved
Extended mode register
Reserved
0
–
E9
0
–
14
BA1
1
E14
E8
0
–
BA0 A12
E13
13
0
E7
0
–
12
E12
Normal operation
All other states reserved
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
11
A11
E11
set to “0”
10
A10
E10
17
A9
E9
9
E6
0
0
1
1
A8
E8
8
E5
0
1
0
1
A7
E7
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A6
E6
6
DS
5
A5
E5
TCSR
4
A4
E4
E2
0
0
0
0
1
1
1
1
1
A3
E3
3
E1
0
0
1
1
0
0
1
1
A2
2
E2
E0
0
1
0
1
0
1
0
1
PASR
1
A1
E1
Partial-Array Self Refresh Coverage
Full array
Half array
Quarter array
Reserved
Reserved
One-eighth array
One-sixteenth array
Reserved
©2005 Micron Technology, Inc. All rights reserved.
A0
0
E0
Register Definition
Address Bus
Extended Mode
Register