MT36HTS1G72PY-667A1 Micron Technology Inc, MT36HTS1G72PY-667A1 Datasheet - Page 13

• Manufacturer Part Number: MT36HTS1G72PY-667A1
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS1G72PY-667A1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 1Gx72
• Total Density: 8GByte
• Access Time (max): 45ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 3.294A
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Serial Presence-Detect
Table 16:
Table 17:
PDF: 09005aef822553c2/Source: 09005aef822553af
HTJ_S36C512_1Gx72.fm - Rev. F 5/07 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to the pull-up
resistance, and the EEPROM does not respond to its slave address.
DD
SS
SS
DD
4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
13
t
WRC) is the time from a valid stop condition of a write
t
Symbol
Symbol
t
t
t
t
HD:DAT
V
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
I
HIGH
DDSPD
LOW
f
WRC
V
I
t
t
CC W
BUF
V
V
I
SCL
I
CC R
AA
DH
I
t
LO
t
SB
t
OL
LI
R
IH
F
IL
I
V
DDSPD
Min
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
–
–
–
–
–
Min
–0.6
0.10
0.05
1.7
1.6
0.4
2
–
× 0.7
Serial Presence-Detect
Max
300
400
0.3
0.9
50
10
©2003 Micron Technology, Inc. All rights reserved.
–
–
–
–
–
–
–
–
–
V
V
DDSPD
DDSPD
Max
3.6
0.4
3
3
4
1
3
Units
+ 0.5
× 0.3
kHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Units
Notes
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4