LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 22

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Figure 17. I/O Cell
Table 10. Shared PTOE Segments
sysIO Standards
Each I/O within a bank is individually configurable based on the V
require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for
V
Lattice
Table 11. Number of I/Os per Bank
CCO,
V
Devices.
REF
and V
TT.
For more information on the sysIO capability, refer to TN1000,
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
Device
Device
Maximum Number of I/Os per Bank (n)
MFBs Associated With Segments
(Y, Z, AA, AB) (AC, AD, AE, AF)
18
(Q, R, S, T) (U, V, W, Z)
(Q, R, S, T) (U, V, W, Z)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
36
68
96
96
CCO
ispXPLD 5000MX Family Data Sheet
and V
REF
settings. Some standards also
sysIO Usage Guidelines for