LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 49

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Boundary Scan Timing Specifications
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BTCP
BTCPH
BTCPL
BTS
BTH
BTRF
BTCO
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
Parameter
TCK [BSCAN] clock pulse width
TCK [BSCAN] clock pulse width high
TCK [BSCAN] clock pulse width low
TCK [BSCAN] setup time
TCK [BSCAN] hold time
TCK [BSCAN] rise/fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
Over Recommended Operating Conditions
Description
45
ispXPLD 5000MX Family Data Sheet
Min
40
20
20
10
50
—
—
—
10
—
—
—
8
8
Max
10
10
10
25
25
25
—
—
—
—
—
—
—
—
mV/ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns