LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 9

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
Figure 3. MFB in SuperWIDE Logic Mode†
Figure 4. Macrocell Slice in Logic Mode AND-Array
68
From
GRP
AND Array
Dual-OR Array
68 Inputs
68 Inputs
Adjacent
Routing
from
from
MFB
From
n-7
Carry-in
n+7
To
Carry-out
Shared PT Reset
PTSA Bypass
Shared PTCLK
PT Clock
PT Preset
PT Reset
Global Reset
PTSA
Carry Out
CLK0
CLK1
CLK2
CLK3
Shared PT Clk En
Shared PT Clk
5
Shared PT Reset
Shared
PT CE
To Routing
ispXPLD 5000MX Family Data Sheet
Macrocell
D
Clk En
Clk
P
Sharing
PTOE
R/L
R
Q
PT OE to
I/O Block
From
I/O Cell
Output
to I/O Block or
Internal Control
(See Pin Table
for Assignments)
GRP