LC5512MV-45FN484C Lattice, LC5512MV-45FN484C Datasheet - Page 25

• Manufacturer Part Number: LC5512MV-45FN484C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 275MHz EECMOS Technology 3.3V 484-Pin BGA
• Manufacturer: Lattice

Specifications of LC5512MV-45FN484C

• Package: 484BGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 4.5 ns
• Number Of User I/os: 253
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 275 MHz
• Number Of Product Terms Per Macro: 160
• Memory Type: EEPROM/SRAM
• Ram Bits: 262144
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysCONFIG Interface
In addition to being able to program the device through the IEEE 1532 interface a microprocessor style interface
(sysCONFIG interface) allows reconfiguration of the SRAM bits within the device. For more information on the sys-
CONFIG capability, refer to TN1026,
ispXP Configuration Usage
Guidelines.
Security Scheme
A programmable security scheme is provided on the ispXPLD 5000MX devices as a deterrent to unauthorized
copying of the array configuration patterns. Once programmed, this bit prevents readback of the programmed pat-
tern by a device programmer, securing proprietary designs from competitors. The security bit also prevents pro-
gramming and verification. The entire device must be erased in order to erase the security bit.
Low Power Consumption
The ispXPLD 5000MX devices use zero power non-volatile cells along with full CMOS design to provide low static
power consumption. The 1.8V core reduces dynamic power consumption compared with devices with higher core
voltages. For information on estimating power consumption, refer to TN1031
Power Estimation in ispXPLD 5000MX
Devices.
Density Migration
The ispXPLD 5000MX family has been designed to ensure that different density devices in the same package have
compatible pin-outs. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high-density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispXPLD 5000MX devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted
in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for board-level testing. The test access port has its
own supply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispXPLD 5000MX family of devices
allows this by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick con-
figuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice’s ispVM™ System programming software can either perform the quick configuration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
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