GS8662Q18GE-250 GSI TECHNOLOGY, GS8662Q18GE-250 Datasheet - Page 7

• Manufacturer Part Number: GS8662Q18GE-250
• Manufacturer: GSI TECHNOLOGY

Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
Alternating Read-Write Operations
SigmaQuad-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for
details.
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied
high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the
Read Enable-bar pin, R, begins a read port deselect cycle.
Rev: 1.08 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Address
BWx
CQ
CQ
W
R
D
C
C
Q
K
K
A
Read A
SigmaQuad-II B2 Double Data Rate SRAM Read First
NOP
7/35
A
B
B
Write B
A+1
B+1
B+1
B
C
D
D
GS8662Q08/09/18/36E-278/250/200/167
Read C Write D
D+1
D+1
D
E
F
F
Read E Write F
F+1
F+1
F
© 2005, GSI Technology
C
G
H
H
Read G Write H
C+1
H+1
H+1
H
E