ATF2500C-20JC Atmel, ATF2500C-20JC Datasheet - Page 3

• Manufacturer Part Number: ATF2500C-20JC
• Description: IC CPLD EE 20NS 44PLCC
• Manufacturer: Atmel
• Series: ATF2500C(L)r

Specifications of ATF2500C-20JC

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 24
• Number Of I /o: 24
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• Package: 44PLCC
• Family Name: ATF2500C
• Device System Gates: 2500
• Maximum Propagation Delay Time: 20 ns
• Number Of User I/os: 24
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 50 MHz
• Number Of Product Terms Per Macro: 12
• Delay Time: 20 ns
• Number Of Programmable I/os: 23
• Operating Supply Voltage: 5 V
• Supply Current: 80 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3. Using the ATF2500C Family’s Many Advanced Features
0777K–PLD–1/24/08
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
• Fully Connected Logic Array – Each array input is always available to every product term.
• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed
• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has
• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.
• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated
• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into
• Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
• User Row (64 bits) – Use to store information such as unit history.
This makes logic placement a breeze.
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also
easily created. These options allow more efficient product term usage.
its input (D/T2) directly back to the logic array. This provides further logic expansion capability
without using precious pin resources.
a dedicated clock product term. This removes the constraint that all registers use the same
clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing
higher performance pin clocking and flexible product term clocking within one design.
Each register has its own clock and reset terms, as well as its own sum term.
input path. Each of the 48 registers has its own feedback term into the array as well. These
features, combined with individual product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
a single term. This provides a fan in of up to 12 product terms per sum term with no speed
penalty.
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
ATF2500C
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