ATF2500C-20JC Atmel, ATF2500C-20JC Datasheet - Page 5

• Manufacturer Part Number: ATF2500C-20JC
• Description: IC CPLD EE 20NS 44PLCC
• Manufacturer: Atmel
• Series: ATF2500C(L)r

Specifications of ATF2500C-20JC

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Macrocells: 24
• Number Of I /o: 24
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 5V
• Memory Type: EEPROM
• Package: 44PLCC
• Family Name: ATF2500C
• Device System Gates: 2500
• Maximum Propagation Delay Time: 20 ns
• Number Of User I/os: 24
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 50 MHz
• Number Of Product Terms Per Macro: 12
• Delay Time: 20 ns
• Number Of Programmable I/os: 23
• Operating Supply Voltage: 5 V
• Supply Current: 80 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Preload and Observability of Registered Outputs
0777K–PLD–1/24/08
The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchro-
nously with either a high or a low. This feature will simplify testing since any state can be forced
into the registers to control test sequencing. A V
priate register high; a V
settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 reg-
isters chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In
this mode, the contents of the buried register bank will appear on the associated outputs when
the OE control signals are active.
Figure 5-1.
Table 5-1.
Level Forced on Odd
PRELOAD Cycle
I/O Pin during
V
V
V
V
IH
IH
IH
IH
/V
/V
/V
/V
IL
IL
IL
IL
Preload Waveforms
Preload Levels
IL
Pin State
Q Select
will force it low, independent of the polarity or other configuration bit
High
High
Low
Low
Even/Odd
Select
High
High
Low
Low
IH
State after
High/Low
Even Q1
level on the odd I/O pins will force the appro-
Cycle
X
X
X
State after
High/Low
Even Q2
Cycle
X
X
X
State after
High/Low
Odd Q1
Cycle
ATF2500C
X
X
X
State after
High/Low
Odd Q2
Cycle
X
X
X
5