EPM240GM100C5N Altera, EPM240GM100C5N Datasheet - Page 3

• Manufacturer Part Number: EPM240GM100C5N
• Description: IC MAX II CPLD 240 LE 100-MBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240GM100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MBGA
• Voltage: 1.8V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 1.8V
• In System Programmable: Yes
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: MBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1726

Chapter 1: Introduction
Features
Table 1–3. MAX II Packages and User I/O Pins
Table 1–4. MAX II TQFP, FineLine BGA, and Micro FineLine BGA Package Sizes
© August 2009 Altera Corporation
EPM240
EPM240G
EPM570
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
Note to
(1) Packages available in lead-free versions only.
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
Device
Package
Table
1–3:
FineLine
BGA
68-Pin
Micro
FineLine
—
—
—
—
54
—
68-Pin
Micro
5 × 5
BGA
(1)
0.5
25
MAX II devices are available in space-saving FineLine BGA, Micro FineLine BGA,
and thin quad flat pack (TQFP) packages (refer to
devices support vertical migration within the same package (for example, you can
migrate between the EPM570, EPM1270, and EPM2210 devices in the 256-pin
FineLine BGA package). Vertical migration means that you can migrate to devices
whose dedicated pins and JTAG pins are the same and power pins are subsets or
supersets for a given package across device densities. The largest density in any
package has the highest number of power pins; you must lay out for the largest
planned density in a package to provide the necessary power pins for migration. For
I/O pin migration across densities, cross reference the available I/O pins using the
device pin-outs for all planned densities of a given package type to identify which
I/O pins can be migrated. The Quartus
and place all pins for you when given a device migration list.
FineLine
100-Pin
BGA
Micro
FineLine
100-Pin
80
76
—
—
80
76
Micro
6 × 6
BGA
0.5
(1)
36
FineLine
100-Pin
FineLine
BGA
100-Pin
11 × 11
80
76
—
—
—
—
BGA
121
1
100-Pin
TQFP
100-Pin
16 × 16
80
76
—
—
—
—
TQFP
256
0.5
144-Pin
TQFP
116
116
144-Pin
22 × 22
—
—
—
—
TQFP
484
0.5
®
II software can automatically cross-reference
FineLine
144-Pin
BGA
Micro
FineLine
144-Pin
116
Micro
—
—
—
—
—
7 × 7
BGA
0.5
49
(1)
Table 1–3
FineLine
256-Pin
BGA
FineLine
256-Pin
Micro
11 × 11
Micro
160
212
160
BGA
—
—
—
121
0.5
and
(1)
Table
FineLine
FineLine
256-Pin
256-Pin
17 × 17
MAX II Device Handbook
BGA
160
212
204
BGA
289
—
—
—
1
1–4). MAX II
FineLine
324-Pin
FineLine
324-Pin
19 × 19
BGA
272
BGA
361
—
—
—
—
—
1
1–3