Z8927320VSG Zilog, Z8927320VSG Datasheet - Page 42

• Manufacturer Part Number: Z8927320VSG
• Description: DSP 20MHZ 16-BIT W/ A/D 44-PLCC
• Manufacturer: Zilog
• Series: Z892x3r
• Type: Fixed Pointr

Specifications of Z8927320VSG

• Interface: SPI, 3-Wire Serial
• Clock Rate: 20MHz
• Non-volatile Memory: OTP (16 kB)
• On-chip Ram: 1kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PERIPHERALS (Continued)
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
TPR—Prescaler Register (Bank13,14/EXT5).
8-bit down counter that holds the current Prescaler Count
Value. It can be read like any other ordinary register. How-
ever, writing to TPR is different than writing to an ordinary
register. A write to TPR causes the lower 8-bit contents of
TPLR to be written into TPR, causing the Prescaler to be
retriggered.
42
Figure 35. TPLR—Prescaler Load Register
15
15
15
Ò1Ó
Figure 34. TMR—Counter Register
Figure 33. TMLR—Load Register
14
Zeros
Timer Reload Value
Bank 13,14/EXT3
Bank 13,14/EXT4
Bank 13,14/EXT2
Timer Register
8 7
Reload Value
Prescaler
TPR is an
0
0
0
Prescaler Operation
The Prescaler section comprises TPLR and TPR, followed
by a divide-by-two flip-flop. This operation generates a 50
percent duty cycle output, TMCLKIN. TPR’s input clock
is the system clock. The maximum prescaler output fre-
quency is 1/2 the system clock frequency.
After TPR is loaded, it decrements at the system clock fre-
quency and generates an output to the divide-by-two flip-
flop. When the count reaches 0, the TPR counter is reloaded
from the lower 8 bits of TPLR Register.
Two other events cause a reloading of the TPR counter:
1. Writing to TPR
2. Reloading TMR, which happens when TMR under-
Note: For C/T Modes 8–11, the external input signal on UI0 or
flows, or when TMR is written.
UI1 is synchronized with TMCLKIN before being ap-
plied to TMR. The external input signal frequency must
be no higher than 1/2 of the TMCLKIN frequency.
Figure 36. TPR—Prescaler Register
7
Bank 13,14/EXT5
8-Bit Counter
TPR
DS000202-DSP0599
0
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