DSPB56721AF Freescale Semiconductor, DSPB56721AF Datasheet - Page 16

• Manufacturer Part Number: DSPB56721AF
• Description: AUDIO PROCESSOR SYMPH 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56721AF

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: External
• On-chip Ram: 744kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11
16
Notes:
1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined
3. Periodically sampled and not 100% tested.
4. RESET duration is measured during the time in which RESET is asserted, V
No.
to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using
fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL
to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.
valid. When V
device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should
minimize this state to the shortest possible duration.
22
DMA Requests Rate
• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Timer, Timer_1
• IRQ, NMI (edge trigger)
shows the reset timing diagram.
DD
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the
Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters
RESET
All Pins
Symphony
Characteristics
™
10
DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
Figure 11. Reset Timing Diagram
Reset Value
11
DD
is valid, and the EXTAL input is active and
Expression
6 × T
7 × T
2 × T
3 × T
C
C
C
C
13
Freescale Semiconductor
Min
—
—
—
—
V
IH
Max
30.0
35.0
10.0
15.0
Unit
ns
ns
ns
ns