DSP56301PW100 Freescale Semiconductor, DSP56301PW100 Datasheet - Page 43

• Manufacturer Part Number: DSP56301PW100
• Description: IC DSP 24BIT FIXED-POINT 208LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56301PW100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (9 kB)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Notes:
No.
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS deassertion
BRW[1–0] = 00
BRW[1–0] = 01
BRW[1–0] = 10
BRW[1–0] = 11
CAS deassertion pulse width
Column address valid to CAS assertion
CAS assertion to column address not valid
Last column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR assertion
CAS assertion to WR deassertion
WR assertion pulse width
Last WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
6.
7.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for the DSP56301.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t
T
BRW[1–0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
At this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table 2-14). However,
DRAM speeds are approaching two-wait-state compatibility.
C
for read-after-read or write-after-write sequences).
Table 2-9.
Characteristics
6
DRAM Page Mode Timings, Two Wait States
5
DSP56301 Technical Data, Rev. 10
Symbol
t
t
t
t
t
t
t
t
RHCP
t
t
t
t
t
t
t
t
WCH
RCH
t
RWL
CWL
WCS
ROH
t
CAC
t
OFF
RSH
CAS
CRP
t
ASC
CAH
RCS
t
t
t
t
RAL
WP
DH
GA
PC
AA
CP
DS
GZ
1.75 × T
3.25 × T
1.25 × T
1.75 × T
2.75 × T
0.25 × T
1.75 × T
1.75 × T
0.75 × T
Not supported
1.5 × T
2.5 × T
1.5 × T
3.5 × T
4.5 × T
6.5 × T
0.5 × T
1.5 × T
2.5 × T
2.5 × T
2.5 × T
Expression
1.25 × T
3 × T
2.75 × T
0.25 × T
T
T
3 × T
C
C
− 4.0
− 4.3
C
C
C
C
C
C
C
C
C
C
C
C
1, 2, 3, 7
C
C
C
C
C
C
C
C
C
− 4.0
OFF
C
C
− 6.5
− 6.5
− 4.0
− 6.0
− 6.0
− 6.0
− 3.7
− 4.2
− 4.5
− 4.3
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 4.3
− 3.0
− 4.0
− 6.5
− 1.5
C
− 4
C
AC Electrical Characteristics
and not t
GZ.
Min
37.5
34.4
17.9
36.6
14.8
37.8
50.3
75.3
11.6
17.9
33.5
11.6
14.6
26.8
30.1
27.0
17.9
27.3
0.0
8.5
2.6
0.1
8.2
0.0
7.9
—
—
—
—
—
80 MHz
Max
PC
12.3
24.8
15.4
3.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
equals 3 ×
Unit
2-17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns