EP2S60F484I4N Altera, EP2S60F484I4N Datasheet - Page 64

• Manufacturer Part Number: EP2S60F484I4N
• Description: IC STRATIX II FPGA 60K 484-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F484I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 334
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 334
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1910; EP2S60F484I4N

PLLs & Clock Networks
2–56
Stratix II Device Handbook, Volume 1
Figure 2–39. External PLL Output Clock Control Blocks
Notes to
(1)
(2)
For the global clock control block, the clock source selection can be
controlled either statically or dynamically. The user has the option of
statically selecting the clock source by using the Quartus II software to set
specific configuration bits in the configuration file (.sof or .pof) or the
user can control the selection dynamically by using internal logic to drive
the multiplexor select inputs. When selecting statically, the clock source
can be set to any of the inputs to the select multiplexor. When selecting
the clock source dynamically, you can either select between two PLL
outputs (such as the C0 or C1 outputs from one PLL), between two PLLs
(such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of
the other PLL), between two clock pins (such as CLK0 or CLK1), or
between a combination of clock pins or PLL outputs. The clock outputs
from corner PLLs cannot be dynamically selected through the global
control block.
For the regional and PLL_OUT clock control block, the clock source
selection can only be controlled statically using configuration bits. Any of
the inputs to the clock select multiplexor can be set as the clock source.
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The
PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
Figure
2–39:
IOE
Internal
Logic
(2)
Outputs (c[5..0])
PLL Counter
PLL_OUT
Enable/
Disable
Pin
6
Internal
Static Clock
Select (1)
Logic
Static Clock Select
(1)
Altera Corporation
May 2007