EPF6024ATC144-3N Altera, EPF6024ATC144-3N Datasheet - Page 26

• Manufacturer Part Number: EPF6024ATC144-3N
• Description: IC FLEX 6000 FPGA 24K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024ATC144-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 117
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 117
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant

FLEX 6000 Programmable Logic Device Family Data Sheet
Output
Configuration
26
Figure 15. SameFrame Pin-Out Example
Table 6
feature.
This section discusses slew-rate control, the MultiVolt I/O interface,
power sequencing, and hot-socketing for FLEX 6000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew-rate that can
be configured for low-noise or high-speed performance. A slower
slew-rate reduces system noise and adds a maximum delay of 6.8 ns. The
fast slew-rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew-rate on
a pin-by-pin basis during design entry or assign a default slew rate to all
pins on a device-wide basis. The slew-rate setting affects only the falling
edge of the output.
Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs
100-Pin FineLine BGA Package
EPF6016A
EPF6024A
lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out
Device
(Reduced I/O Count or
Logic Requirements)
Designed for 256-Pin FineLine BGA Package
FineLine
100-Pin
BGA
100-Pin FineLine BGA
Printed Circuit Board
v
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
FineLine
256-Pin
256-Pin FineLine BGA
BGA
Altera Corporation
v
v