EPF6024ATC144-3N Altera, EPF6024ATC144-3N Datasheet - Page 6

• Manufacturer Part Number: EPF6024ATC144-3N
• Description: IC FLEX 6000 FPGA 24K 144-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6024ATC144-3N

• Number Of Logic Elements/cells: 1960
• Number Of Labs/clbs: 196
• Number Of I /o: 117
• Number Of Gates: 24000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-TQFP, 144-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 24000
• Number Of Logic Blocks/elements: 1960
• # I/os (max): 117
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1960
• Device System Gates: 24000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Compliant

FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 1. OptiFLEX Architecture Block Diagram
6
IOEs
Column FastTrack
Interconnect
FLEX 6000 devices provide four dedicated, global inputs that drive the
control inputs of the flipflops to ensure efficient distribution of high-
speed, low-skew control signals. These inputs use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect. These inputs can also be driven by internal logic, providing
an ideal solution for a clock divider or an internally generated
asynchronous clear signal that clears many registers in the device. The
dedicated global routing structure is built into the device, eliminating the
need to create a clock tree.
Logic Array Block
An LAB consists of ten LEs, their associated carry and cascade chains, the
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure of the FLEX 6000 architecture, and facilitates
efficient routing with optimum device utilization and high performance.
Local Interconnect
(Each LAB accesses
two local interconnect
areas.)
Column FastTrack
Interconnect
Row FastTrack
Interconnect
IOEs
Logic Elements
Row FastTrack
Interconnect
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