EP4CE40F29I7N Altera, EP4CE40F29I7N Datasheet - Page 27

• Manufacturer Part Number: EP4CE40F29I7N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29I7N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 39600
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Periphery Performance
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices
© December 2010 Altera Corporation
f
(input clock
frequency)
HSCLK
Symbol
f
1
Modes
×10
×8
×7
×4
×2
×1
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to
Performance Specifications
Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 1–31
For definitions of high-speed timing specifications, refer to
t
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
Symbol
JSXZ
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
Min Typ Max Min Typ
10
10
10
10
10
10
Table
Update register valid output to high impedance
through
—
—
—
—
—
—
C6
1–30:
180
180
180
180
180
360
Table 1–36
10
10
10
10
10
10
of the External Memory Interfaces Handbook.
C7, I7
—
—
—
—
—
—
list the high-speed I/O timing for Cyclone IV devices.
Parameter
155.5
155.5
155.5
155.5
155.5
Max
311
Min
10
10
10
10
10
10
“JTAG Waveform”
C8, A7
(Note
Typ
—
—
—
—
—
—
1), (2),
155.5
155.5
155.5
155.5
155.5
Max
311
(Note 1)
in
(4)
Cyclone IV Device Handbook, Volume 3
“Glossary” on page
Min Typ
“Glossary” on page
10
10
10
10
10
10
(Part 1 of 2)—Preliminary
(Part 2 of 2)—Preliminary
Section III: System
C8L, I8L
—
—
—
—
—
—
Min
—
155.5
155.5
155.5
155.5
155.5
Max
311
1–38.
Max
25
Min Typ
10
10
10
10
10
10
1–38.
Unit
ns
1–27
—
—
—
—
—
—
C9L
132.5
132.5
132.5
132.5
132.5
Max
265
MHz
MHz
MHz
MHz
MHz
MHz
Unit