EP4CE40F29I7N Altera, EP4CE40F29I7N Datasheet - Page 31

• Manufacturer Part Number: EP4CE40F29I7N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29I7N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 39600
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–34. True LVDS Transmitter Timing Specifications for Cyclone IV Devices
Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices
—Preliminary
© December 2010 Altera Corporation
t
Notes to
(1) Cyclone IV E—true LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6.
(2) t
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7,
f
clock
frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.
(2) t
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7,
LOCK
HSCLK
DUTY
LOCK
Symbol
Symbol
(2)
(2)
Cyclone IV GX—true LVDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6.
and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
LOCK
(input
LOCK
Table
is the time required for the PLL to lock from the end-of-device configuration.
Table
is the time required for the PLL to lock from the end-of-device configuration.
1–34:
1–35:
Modes
Modes
×10
×10
—
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
Min
Min
100
—
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
C6
C6
402.5
402.5
Max
Max
320
320
320
320
320
640
640
640
640
640
200
500
55
1
1
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
C7, I7
C7, I7
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
200
500
Max
55
1
1
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
C8, A7
C8, A7
402.5
402.5
Max
275
275
275
275
275
550
550
550
550
550
200
550
Max
55
1
1
(Note
(Note
1),
Min
100
Min
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
C8L, I8L
(3)
Cyclone IV Device Handbook, Volume 3
C8L, I8L
1),
(Part 2 of 2) —Preliminary
(3)
Max
275
275
275
275
275
362
550
550
550
550
550
362
200
600
55
Max
1
1
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
Min
—
C9L
C9L
Max
250
250
250
250
250
265
500
500
500
500
500
265
200
700
55
Max
1
1–31
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
Unit
%
ps
ps
ms